4 #define VDP_DATA_PORT 0xc00000
5 #define VDP_CTL_PORT 0xc00004
8 #define VDP_VRAM 0x40000000
9 #define VDP_CRAM 0xc0000000
10 #define VDP_VSRAM 0x40000010
15 #define REG16PTR(addr) (*(volatile uint16_t*)(addr))
16 #define REG32PTR(addr) (*(volatile uint32_t*)(addr))
18 #define Z80_MEMMODE REG16PTR(0xa11000)
19 #define Z80_BUSREQ REG16PTR(0xa11100)
20 #define Z80_RESET REG16PTR(0xa11200)
21 #define Z80_MEM ((uint8_t*)0xa00000)
23 #define VDP_DATA REG16PTR(VDP_DATA_PORT)
24 #define VDP_CTL REG16PTR(VDP_CTL_PORT)
25 #define VDP_CTL32 REG32PTR(VDP_CTL_PORT)
26 #define VDP_STAT VDP_CTL
29 #define VDP_REG_MODE1 0
30 #define VDP_REG_MODE2 1
31 #define VDP_REG_NAMEA 2
32 #define VDP_REG_NAMEW 3
33 #define VDP_REG_NAMEB 4
35 #define VDP_REG_BGCOL 7
36 #define VDP_REG_HINTR 10
37 #define VDP_REG_MODE3 11
38 #define VDP_REG_MODE4 12
39 #define VDP_REG_HSCROLL 13
40 #define VDP_REG_AUTOINC 15
41 #define VDP_REG_SCROLLSZ 16
42 #define VDP_REG_WINX 17
43 #define VDP_REG_WINY 18
44 #define VDP_REG_DMACNTL 19
45 #define VDP_REG_DMACNTH 20
46 #define VDP_REG_DMASRCL 21
47 #define VDP_REG_DMASRCM 22
48 #define VDP_REG_DMASRCH 23
50 #define VDP_ST_PAL 0x001
51 #define VDP_ST_DMA 0x002
52 #define VDP_ST_HBLANK 0x004
53 #define VDP_ST_VBLANK 0x008
54 #define VDP_ST_ODDFRM 0x010
55 #define VDP_ST_COL 0x020
56 #define VDP_ST_SPROVF 0x040
57 #define VDP_ST_VINTR 0x080
58 #define VDP_ST_FULL 0x100
59 #define VDP_ST_EMPT 0x200
61 #define VDP_M1_INIT 0x04
62 #define VDP_M1_HVSTOP 0x02
63 #define VDP_M1_HINTR 0x10
65 #define VDP_M2_INIT 0x04
66 #define VDP_M2_V30 0x08
67 #define VDP_M2_DMA 0x10
68 #define VDP_M2_VINTR 0x20
69 #define VDP_M2_DISP 0x40
71 #define VDP_NA_ADDR(x) (((x) >> 14) & 0x38)
72 #define VDP_NW_ADDR(x) (((x) >> 14) & 0x3e)
73 #define VDP_NB_ADDR(x) ((x) >> 17)
74 #define VDP_SPRTAB_ADDR(x) ((x) >> 9)
75 #define VDP_HSTAB_ADDR(x) ((x) >> 10)
77 #define VDP_BGCOL(pal, col) (((pal) << 4) | (col))
79 #define VDP_M3_HFULL 0
80 #define VDP_M3_HCELL 0x02
81 #define VDP_M3_HLINE 0x03
82 #define VDP_M3_VFULL 0
83 #define VDP_M3_V2CELL 0x04
84 #define VDP_M3_EXTINTR 0x08
86 #define VDP_M4_H40 0x81
87 #define VDP_M4_ILACE 0x02
88 #define VDP_M4_ILACE2X 0x06
89 #define VDP_M4_SHAD 0x08
92 #define VDP_SCR_H64 0x01
93 #define VDP_SCR_H128 0x03
95 #define VDP_SCR_V64 0x10
96 #define VDP_SCR_V128 0x30
98 #define VDP_WINX_RIGHT 0x80
99 #define VDP_WINY_DOWN 0x80
101 #define VDP_DMA_MEM 0
102 #define VDP_DMA_FILL 0x80
103 #define VDP_DMA_COPY 0xc0
105 #endif /* HWREGS_H_ */