added debug output on exceptions

[mdlife] / src / hwregs.h

#ifndef HWREGS_H_
#define HWREGS_H_

#define VDP_DATA_PORT   0xc00000
#define VDP_CTL_PORT    0xc00004

#define IO_DATA1_PORT   0xa10003
#define IO_DATA2_PORT   0xa10005
#define IO_DATA3_PORT   0xa10007
#define IO_CTL1_PORT    0xa10009
#define IO_CTL2_PORT    0xa1000b
#define IO_CTL3_PORT    0xa1000d
#define IO_TX1_PORT             0xa1000f
#define IO_RX1_PORT             0xa10011
#define IO_SCTL1_PORT   0xa10013
#define IO_TX2_PORT             0xa10015
#define IO_RX2_PORT             0xa10017
#define IO_SCTL2_PORT   0xa10019
#define IO_TX3_PORT             0xa1001b
#define IO_RX3_PORT             0xa1001d
#define IO_SCTL3_PORT   0xa1001f

/* VDP access type */
#define VDP_VRAM        0x40000000
#define VDP_CRAM        0xc0000000
#define VDP_VSRAM       0x40000010

#define VDP_VRAM_DMA    0x40000080
#define VDP_CRAM_DMA    0xc0000080
#define VDP_VSRAM_DMA   0x40000090

#ifndef ASM
#include <stdint.h>

#define REG16PTR(addr)  (*(volatile uint16_t*)(addr))
#define REG32PTR(addr)  (*(volatile uint32_t*)(addr))

#define Z80_MEMMODE                     REG16PTR(0xa11000)
#define Z80_BUSREQ                      REG16PTR(0xa11100)
#define Z80_RESET                       REG16PTR(0xa11200)
#define Z80_MEM                         ((uint8_t*)0xa00000)

#define VDP_DATA                REG16PTR(VDP_DATA_PORT)
#define VDP_CTL                 REG16PTR(VDP_CTL_PORT)
#define VDP_CTL32               REG32PTR(VDP_CTL_PORT)
#define VDP_STAT                VDP_CTL

#define IO_DATA1                REG16PTR(IO_DATA1_PORT)
#define IO_DATA2                REG16PTR(IO_DATA2_PORT)
#define IO_DATA3                REG16PTR(IO_DATA3_PORT)
#define IO_CTL1                 REG16PTR(IO_CTL1_PORT)
#define IO_CTL2                 REG16PTR(IO_CTL2_PORT)
#define IO_CTL3                 REG16PTR(IO_CTL3_PORT)
#define IO_TX1                  REG16PTR(IO_TX1_PORT)
#define IO_RX1                  REG16PTR(IO_RX1_PORT)
#define IO_SCTL1                REG16PTR(IO_SCTL1_PORT)
#define IO_TX2                  REG16PTR(IO_TX2_PORT)
#define IO_RX2                  REG16PTR(IO_RX2_PORT)
#define IO_SCTL2                REG16PTR(IO_SCTL2_PORT)
#define IO_TX3                  REG16PTR(IO_TX3_PORT)
#define IO_RX3                  REG16PTR(IO_RX3_PORT)
#define IO_SCTL3                REG16PTR(IO_SCTL3_PORT)

#endif  /* !def ASM */


/* --- VDP registers --- */

#define VDP_REG_MODE1           0
#define VDP_REG_MODE2           1
#define VDP_REG_NAMEA           2
#define VDP_REG_NAMEW           3
#define VDP_REG_NAMEB           4
#define VDP_REG_SPR                     5
#define VDP_REG_BGCOL           7
#define VDP_REG_HINTR           10
#define VDP_REG_MODE3           11
#define VDP_REG_MODE4           12
#define VDP_REG_HSCROLL         13
#define VDP_REG_AUTOINC         15
#define VDP_REG_SCROLLSZ        16
#define VDP_REG_WINX            17
#define VDP_REG_WINY            18
#define VDP_REG_DMACNTL         19
#define VDP_REG_DMACNTH         20
#define VDP_REG_DMASRCL         21
#define VDP_REG_DMASRCM         22
#define VDP_REG_DMASRCH         23

#define VDP_ST_PAL              0x001
#define VDP_ST_DMA              0x002
#define VDP_ST_HBLANK   0x004
#define VDP_ST_VBLANK   0x008
#define VDP_ST_ODDFRM   0x010
#define VDP_ST_COL              0x020
#define VDP_ST_SPROVF   0x040
#define VDP_ST_VINTR    0x080
#define VDP_ST_FULL             0x100
#define VDP_ST_EMPT             0x200

#define VDP_M1_INIT             0x04
#define VDP_M1_HVSTOP   0x02
#define VDP_M1_HINTR    0x10

#define VDP_M2_INIT             0x04
#define VDP_M2_V30              0x08
#define VDP_M2_DMA              0x10
#define VDP_M2_VINTR    0x20
#define VDP_M2_DISP             0x40

#define VDP_NA_ADDR(x)  (((x) >> 10) & 0x38)
#define VDP_NW_ADDR(x)  (((x) >> 10) & 0x3e)
#define VDP_NB_ADDR(x)  ((x) >> 13)
#define VDP_SPRTAB_ADDR(x)      ((x) >> 9)
#define VDP_HSTAB_ADDR(x)       ((x) >> 10)

#define VDP_ADDR_INVAL  0x10000

#define VDP_BGCOL(pal, col)     (((pal) << 4) | (col))

#define VDP_M3_HFULL    0
#define VDP_M3_HCELL    0x02
#define VDP_M3_HLINE    0x03
#define VDP_M3_VFULL    0
#define VDP_M3_V2CELL   0x04
#define VDP_M3_EXTINTR  0x08

#define VDP_M4_H40              0x81
#define VDP_M4_ILACE    0x02
#define VDP_M4_ILACE2X  0x06
#define VDP_M4_SHAD             0x08

#define VDP_SCR_H32             0
#define VDP_SCR_H64             0x01
#define VDP_SCR_H128    0x03
#define VDP_SCR_V32             0
#define VDP_SCR_V64             0x10
#define VDP_SCR_V128    0x30

#define VDP_WINX_RIGHT  0x80
#define VDP_WINY_DOWN   0x80

#define VDP_DMA_MEM             0
#define VDP_DMA_FILL    0x80
#define VDP_DMA_COPY    0xc0

/* --- I/O registers --- */

#define IO_BIT_UP               0x01
#define IO_BIT_DOWN             0x02
#define IO_BIT_LEFT             0x04
#define IO_BIT_RIGHT    0x08
#define IO_BIT_TL               0x10
#define IO_BIT_TR               0x20
#define IO_BIT_TH               0x40

#define IO_CTL_INT              0x80

#define IO_SCTL_TXFULL  0x01
#define IO_SCTL_RXRDY   0x02
#define IO_SCTL_RXERR   0x04
#define IO_SCTL_RXINT   0x08
#define IO_SCTL_SEROUT  0x10
#define IO_SCTL_SERIN   0x20
#define IO_SCTL_B4800   0
#define IO_SCTL_B2400   0x40
#define IO_SCTL_B1200   0x80
#define IO_SCTL_B300    0xc0

#endif  /* HWREGS_H_ */