4 #define VDP_DATA_PORT 0xc00000
5 #define VDP_CTL_PORT 0xc00004
7 #define IO_DATA1_PORT 0xa10003
8 #define IO_DATA2_PORT 0xa10005
9 #define IO_DATA3_PORT 0xa10007
10 #define IO_CTL1_PORT 0xa10009
11 #define IO_CTL2_PORT 0xa1000b
12 #define IO_CTL3_PORT 0xa1000d
13 #define IO_TX1_PORT 0xa1000f
14 #define IO_RX1_PORT 0xa10011
15 #define IO_SCTL1_PORT 0xa10013
16 #define IO_TX2_PORT 0xa10015
17 #define IO_RX2_PORT 0xa10017
18 #define IO_SCTL2_PORT 0xa10019
19 #define IO_TX3_PORT 0xa1001b
20 #define IO_RX3_PORT 0xa1001d
21 #define IO_SCTL3_PORT 0xa1001f
24 #define VDP_VRAM 0x40000000
25 #define VDP_CRAM 0xc0000000
26 #define VDP_VSRAM 0x40000010
28 #define VDP_VRAM_DMA 0x40000080
29 #define VDP_CRAM_DMA 0xc0000080
30 #define VDP_VSRAM_DMA 0x40000090
32 #define VDP_RGB(r, g, b) \
33 (((uint16_t)(r) & 0xe) | \
34 (((uint16_t)(g) & 0xe) << 4) | \
35 (((uint16_t)(b) & 0xe) << 8))
41 #define REG16PTR(addr) (*(volatile uint16_t*)(addr))
42 #define REG32PTR(addr) (*(volatile uint32_t*)(addr))
44 #define Z80_MEMMODE REG16PTR(0xa11000)
45 #define Z80_BUSREQ REG16PTR(0xa11100)
46 #define Z80_RESET REG16PTR(0xa11200)
47 #define Z80_MEM ((volatile uint8_t*)0xa00000)
49 #define VDP_DATA REG16PTR(VDP_DATA_PORT)
50 #define VDP_CTL REG16PTR(VDP_CTL_PORT)
51 #define VDP_CTL32 REG32PTR(VDP_CTL_PORT)
52 #define VDP_STAT VDP_CTL
54 #define IO_DATA1 REG16PTR(IO_DATA1_PORT)
55 #define IO_DATA2 REG16PTR(IO_DATA2_PORT)
56 #define IO_DATA3 REG16PTR(IO_DATA3_PORT)
57 #define IO_CTL1 REG16PTR(IO_CTL1_PORT)
58 #define IO_CTL2 REG16PTR(IO_CTL2_PORT)
59 #define IO_CTL3 REG16PTR(IO_CTL3_PORT)
60 #define IO_TX1 REG16PTR(IO_TX1_PORT)
61 #define IO_RX1 REG16PTR(IO_RX1_PORT)
62 #define IO_SCTL1 REG16PTR(IO_SCTL1_PORT)
63 #define IO_TX2 REG16PTR(IO_TX2_PORT)
64 #define IO_RX2 REG16PTR(IO_RX2_PORT)
65 #define IO_SCTL2 REG16PTR(IO_SCTL2_PORT)
66 #define IO_TX3 REG16PTR(IO_TX3_PORT)
67 #define IO_RX3 REG16PTR(IO_RX3_PORT)
68 #define IO_SCTL3 REG16PTR(IO_SCTL3_PORT)
73 /* --- VDP registers --- */
75 #define VDP_REG_MODE1 0
76 #define VDP_REG_MODE2 1
77 #define VDP_REG_NAMEA 2
78 #define VDP_REG_NAMEW 3
79 #define VDP_REG_NAMEB 4
81 #define VDP_REG_BGCOL 7
82 #define VDP_REG_HINTR 10
83 #define VDP_REG_MODE3 11
84 #define VDP_REG_MODE4 12
85 #define VDP_REG_HSCROLL 13
86 #define VDP_REG_AUTOINC 15
87 #define VDP_REG_SCROLLSZ 16
88 #define VDP_REG_WINX 17
89 #define VDP_REG_WINY 18
90 #define VDP_REG_DMACNTL 19
91 #define VDP_REG_DMACNTH 20
92 #define VDP_REG_DMASRCL 21
93 #define VDP_REG_DMASRCM 22
94 #define VDP_REG_DMASRCH 23
96 #define VDP_ST_PAL 0x001
97 #define VDP_ST_DMA 0x002
98 #define VDP_ST_HBLANK 0x004
99 #define VDP_ST_VBLANK 0x008
100 #define VDP_ST_ODDFRM 0x010
101 #define VDP_ST_COL 0x020
102 #define VDP_ST_SPROVF 0x040
103 #define VDP_ST_VINTR 0x080
104 #define VDP_ST_FULL 0x100
105 #define VDP_ST_EMPT 0x200
107 #define VDP_M1_INIT 0x04
108 #define VDP_M1_HVSTOP 0x02
109 #define VDP_M1_HINTR 0x10
111 #define VDP_M2_INIT 0x04
112 #define VDP_M2_V30 0x08
113 #define VDP_M2_DMA 0x10
114 #define VDP_M2_VINTR 0x20
115 #define VDP_M2_DISP 0x40
117 #define VDP_NA_ADDR(x) (((x) >> 10) & 0x38)
118 #define VDP_NW_ADDR(x) (((x) >> 10) & 0x3e)
119 #define VDP_NB_ADDR(x) (((x) >> 13) & 7)
120 #define VDP_SPRTAB_ADDR(x) ((x) >> 9)
121 #define VDP_HSTAB_ADDR(x) ((x) >> 10)
123 #define VDP_ADDR_INVAL 0x10000
125 #define VDP_BGCOL(pal, col) (((pal) << 4) | (col))
127 #define VDP_M3_HFULL 0
128 #define VDP_M3_HCELL 0x02
129 #define VDP_M3_HLINE 0x03
130 #define VDP_M3_VFULL 0
131 #define VDP_M3_V2CELL 0x04
132 #define VDP_M3_EXTINTR 0x08
134 #define VDP_M4_H40 0x81
135 #define VDP_M4_ILACE 0x02
136 #define VDP_M4_ILACE2X 0x06
137 #define VDP_M4_SHAD 0x08
139 #define VDP_SCR_H32 0
140 #define VDP_SCR_H64 0x01
141 #define VDP_SCR_H128 0x03
142 #define VDP_SCR_V32 0
143 #define VDP_SCR_V64 0x10
144 #define VDP_SCR_V128 0x30
146 #define VDP_WINX_RIGHT 0x80
147 #define VDP_WINY_DOWN 0x80
149 #define VDP_DMA_MEM 0
150 #define VDP_DMA_FILL 0x80
151 #define VDP_DMA_COPY 0xc0
153 /* --- I/O registers --- */
155 #define IO_BIT_UP 0x01
156 #define IO_BIT_DOWN 0x02
157 #define IO_BIT_LEFT 0x04
158 #define IO_BIT_RIGHT 0x08
159 #define IO_BIT_TL 0x10
160 #define IO_BIT_TR 0x20
161 #define IO_BIT_TH 0x40
163 #define IO_CTL_INT 0x80
165 #define IO_SCTL_TXFULL 0x01
166 #define IO_SCTL_RXRDY 0x02
167 #define IO_SCTL_RXERR 0x04
168 #define IO_SCTL_RXINT 0x08
169 #define IO_SCTL_SEROUT 0x10
170 #define IO_SCTL_SERIN 0x20
171 #define IO_SCTL_B4800 0
172 #define IO_SCTL_B2400 0x40
173 #define IO_SCTL_B1200 0x80
174 #define IO_SCTL_B300 0xc0
176 #endif /* HWREGS_H_ */