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[mdlife] / src / z80 / sndregs.inc
1 YMADDR  equ $4000
2 YMDATA  equ $4001
3 YMADDR2 equ $4002
4 YMDATA2 equ $4003
5
6 YM_LFO          equ $22
7 YM_TIMERA_L     equ $24
8 YM_TIMERA_H     equ $25
9 YM_TIMERB       equ $26
10 YM_MODE         equ $27
11 YM_OPER         equ $28
12 YM_DAC          equ $2a
13 YM_DACEN        equ $2b
14
15 YM_DT1MUL_OP1   equ $30
16 YM_DT1MUL_OP2   equ $34
17 YM_DT1MUL_OP3   equ $38
18 YM_DT1MUL_OP4   equ $3c
19 YM_TL_OP1       equ $40
20 YM_TL_OP2       equ $44
21 YM_TL_OP3       equ $48
22 YM_TL_OP4       equ $4c
23 YM_RSAR_OP1     equ $50
24 YM_RSAR_OP2     equ $54
25 YM_RSAR_OP3     equ $58
26 YM_RSAR_OP4     equ $5c
27 YM_AMD1R_OP1    equ $60
28 YM_AMD1R_OP2    equ $64
29 YM_AMD1R_OP3    equ $68
30 YM_AMD1R_OP4    equ $6c
31 YM_D2R_OP1      equ $70
32 YM_D2R_OP2      equ $74
33 YM_D2R_OP3      equ $78
34 YM_D2R_OP4      equ $7c
35 YM_D1LRR_OP1    equ $80
36 YM_D1LRR_OP2    equ $84
37 YM_D1LRR_OP3    equ $88
38 YM_D1LRR_OP4    equ $8c
39 YM_SSGEG_OP1    equ $90
40 YM_SSGEG_OP2    equ $94
41 YM_SSGEG_OP3    equ $98
42 YM_SSGEG_OP4    equ $9c
43
44 YM_FREQ         equ $a0
45 YM_BLOCKFREQ    equ $a4
46 YM_CH3SUPFREQ   equ $a8
47 YM_CH3SUPBLKFREQ        equ $ac
48 YM_FEEDBALG     equ $b0
49 YM_LRAMSFMS     equ $b4
50
51 ; vi:ft=z80: