; interrupt entry routines
	cpu 8086
	bits 16
	section .text

extern dispatch_intr

%macro INTR_ENTRY 2
global intr_entry_%2
intr_entry_%2:
	push bp
	push ax
	push bp
	mov bp, sp
	mov ax, %1
	mov [bp + 4], ax
	pop bp
	pop ax
	jmp intr_entry_common
%endmacro

intr_entry_common:
	push ax
	mov ax, sp
	add ax, 2
	push cx
	push dx
	push bx
	push ax	; saved sp
	push bp
	push si
	push di
	call dispatch_intr
	pop di
	pop si
	pop bp
	pop bx	; throw away saved sp
	pop bx
	pop dx
	pop cx
	pop ax
	add sp, 2	; remove interrupt number from the stack
	iret

; CPU exceptions
INTR_ENTRY 0, div
INTR_ENTRY 1, trap
INTR_ENTRY 2, nmi
INTR_ENTRY 3, break
INTR_ENTRY 4, ovf
INTR_ENTRY 5, bound
INTR_ENTRY 6, ill
; IRQs
INTR_ENTRY 8, irq0
INTR_ENTRY 9, irq1
INTR_ENTRY 10, irq2
INTR_ENTRY 11, irq3
INTR_ENTRY 12, irq4
INTR_ENTRY 13, irq5
INTR_ENTRY 14, irq6
INTR_ENTRY 15, irq7

	; int86 implementation
	global int86
int86:
	push bp
	mov bp, sp
	push bx
	push si
	push di
	pushf

	mov ax, [bp + 4]
	mov [cs:.intop + 1], al	; modify int instruction

	mov [saved_sp], sp
	mov sp, [bp + 6]
	pop ax
	pop bx
	pop cx
	pop dx
	pop si
	pop di
	popf
	mov sp, [saved_sp]

.intop:	int 0xff

	mov [saved_ax], ax
	pushf
	pop ax
	mov sp, [bp + 8]
	add sp, 14	; sp at end of outregs
	push ax		; flags
	mov ax, [saved_ax]
	push di
	push si
	push dx
	push cx
	push bx
	push ax

	mov sp, [saved_sp]
	popf
	pop di
	pop si
	pop bx
	pop bp
	ret

saved_sp dw 0
saved_ax dw 0

; vi:ts=8 sts=8 sw=8 ft=nasm: