.text

#include "hwregs.h"

	.globl vdp_init
vdp_init:
	| initialize registers
	move.l #def_reg_tab, %a0
	clr.w %d1
0:	move.w %d1, %d0
	lsl.w #8, %d0
	or.w #0x8000, %d0
	move.b (%a0)+, %d0
	move.w %d0, VDP_CTL_PORT	| VDP_CTL = 0x8000 | (reg << 8) | val
	add.w #1, %d1
	cmp.w def_reg_tab_size, %d1
	bne.s 0b

	| clear VRAM
	clr.l %d0
	move.l #VDP_VRAM, %d1
	bsr setup_addr
	clr.w %d0
	move.w #0xffff, %d1
0:	move.w %d0, VDP_DATA_PORT
	dbra.w %d1, 0b
	
	rts


	| address in d0, type in d1
setup_addr:
	lsl.l #2, %d0
	lsr.w #2, %d0
	swap %d0
	or.l %d1, %d0
	move.l %d0, VDP_CTL_PORT
	rts

	.globl vdp_setcolor
vdp_setcolor:
	move.l 4(%sp), %d0	| palette number
	lsl.l #4, %d0
	add.l 8(%sp), %d0	| add index
	lsl.l #1, %d0
	move.l #VDP_CRAM, %d1
	bsr setup_addr
	move.w 22(%sp), %d0	| blue
	lsl.w #4, %d0
	or.w 18(%sp), %d0	| green
	lsl.w #4, %d0
	or.w 14(%sp), %d0	| red
	and.w #0x0eee, %d0
	move.w %d0, VDP_DATA_PORT
	rts

	.section .rodata
def_reg_tab:
	.byte VDP_M1_INIT			| 0: mode 1
	.byte VDP_M2_INIT + VDP_M2_DISP		| 1: mode 2
	.byte VDP_NA_ADDR(0xc000)		| 2: scroll A nametable addr.
	.byte VDP_NW_ADDR(VDP_ADDR_INVAL)	| 3: window nametable addr.
	.byte VDP_NB_ADDR(0xd000)		| 4: scroll B nametable addr.
	.byte VDP_SPRTAB_ADDR(0xe000)		| 5: sprite table addr.
	.byte 0
	.byte 0					| 7: bg color
	.byte 0, 0
	.byte 0					| 10: horiz. interrupt interval
	.byte 0					| 11: mode 3
	.byte VDP_M4_H40			| 12: mode 4
	.byte 0					| 13: hscroll table addr.
	.byte 0
	.byte 2					| 15: autoincrement 2 bytes
	.byte VDP_SCR_H64			| 16: scroll size (64x32)
	.byte 0, 0				| 17,18: win x/y pos
	.byte 0, 0, 0, 0, 0			| 19-23: DMA regs
def_reg_tab_end:
	.align 2
def_reg_tab_size:
	.word def_reg_tab_end - def_reg_tab

	
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