include "sndregs.inc"

	section .vect
	jr main		; RST 0
	dc 6,0
	dc 6*8, 0	; RST [1, 7]
	jp vblank_isr

TESTDATA_LEN equ 43
IPC	equ $1ffc

	section .text
main:	di
	halt	; XXX
	im 1
	ld sp, $1ff0
	call init
	; iy is left with YMADDR
	ld (iy), YM_OPER
	ld (iy+1), $f0	; key on
	ei
mainloop:
	;halt		; wait for interrupt
	ld a, (frame)
	ld b, a		; b: cur frame
	ld a, (prev)	; a: prev frame
	xor b
	bit 7, a
	ld a, b
	ld (prev), a
	jr z, mainloop

	bit 7, a	; 0: play, 1: stop
	jr z, .keyon
	ld (iy), YM_OPER
	ld (iy+1), 0	; key off
	jr mainloop
.keyon:	ld (iy), YM_OPER
	ld (iy+1), $f0	; key on
	jr mainloop

init:
	ld ix, testdata
	ld iy, YMADDR
	ld b, TESTDATA_LEN
.loop:	call ymwait
	ld a, (ix)
	ld (iy), a	; select reg
	inc ix
	call ymwait
	ld a, (ix)
	ld (iy+1), a	; write reg
	inc ix
	djnz .loop
	ret

ymwait:
	ld a, (YMADDR)
	bit 7, a
	jr nz, ymwait
	ret

vblank_isr:
	ex af, af'
	exx

	ld hl, frame
	inc (hl)
	ld a, (hl)
	ld (IPC+1), a

	exx
	ex af, af'
	ei
	ret


frame:	db 0
prev:	db 0


testdata:
	db YM_LFO, 0
	db YM_MODE, 0
	db YM_OPER, 0
	db YM_OPER, 1
	db YM_OPER, 2
	db YM_OPER, 3
	db YM_OPER, 4
	db YM_OPER, 5
	db YM_OPER, 6
	db YM_DACEN, 0
	db YM_DT1MUL_OP1, $71
	db YM_DT1MUL_OP2, $0d
	db YM_DT1MUL_OP3, $33
	db YM_DT1MUL_OP4, $01
	db YM_TL_OP1, $23
	db YM_TL_OP2, $2d
	db YM_TL_OP3, $26
	db YM_TL_OP4, 0
	db YM_RSAR_OP1, $5f
	db YM_RSAR_OP2, $99
	db YM_RSAR_OP3, $5f
	db YM_RSAR_OP4, $94
	db YM_AMD1R_OP1, 5
	db YM_AMD1R_OP2, 5
	db YM_AMD1R_OP3, 5
	db YM_AMD1R_OP3, 7
	db YM_D2R_OP1, 2
	db YM_D2R_OP2, 2
	db YM_D2R_OP3, 2
	db YM_D2R_OP4, 2
	db YM_D1LRR_OP1, $11
	db YM_D1LRR_OP2, $11
	db YM_D1LRR_OP3, $11
	db YM_D1LRR_OP4, $a6
	db YM_SSGEG_OP1, 0
	db YM_SSGEG_OP2, 0
	db YM_SSGEG_OP3, 0
	db YM_SSGEG_OP4, 0
	db YM_FEEDBALG, $32
	db YM_LRAMSFMS, $c0
	db YM_OPER, 0
	db YM_BLOCKFREQ, $22
	db YM_FREQ, $69

; vi:ft=z80: