input handling

[mdlife] / src / hwregs.h

diff --git a/src/hwregs.h b/src/hwregs.h
index 2838026..8e21f25 100644 (file)
--- a/src/hwregs.h
+++ b/src/hwregs.h
@@ -4,6 +4,22 @@
 #define VDP_DATA_PORT  0xc00000
 #define VDP_CTL_PORT   0xc00004
 
+#define IO_DATA1_PORT  0xa10003
+#define IO_DATA2_PORT  0xa10005
+#define IO_DATA3_PORT  0xa10007
+#define IO_CTL1_PORT   0xa10009
+#define IO_CTL2_PORT   0xa1000b
+#define IO_CTL3_PORT   0xa1000d
+#define IO_TX1_PORT            0xa1000f
+#define IO_RX1_PORT            0xa10011
+#define IO_SCTL1_PORT  0xa10013
+#define IO_TX2_PORT            0xa10015
+#define IO_RX2_PORT            0xa10017
+#define IO_SCTL2_PORT  0xa10019
+#define IO_TX3_PORT            0xa1001b
+#define IO_RX3_PORT            0xa1001d
+#define IO_SCTL3_PORT  0xa1001f
+
 /* VDP access type */
 #define VDP_VRAM       0x40000000
 #define VDP_CRAM       0xc0000000
@@ -28,8 +44,28 @@
 #define VDP_CTL                        REG16PTR(VDP_CTL_PORT)
 #define VDP_CTL32              REG32PTR(VDP_CTL_PORT)
 #define VDP_STAT               VDP_CTL
+
+#define IO_DATA1               REG16PTR(IO_DATA1_PORT)
+#define IO_DATA2               REG16PTR(IO_DATA2_PORT)
+#define IO_DATA3               REG16PTR(IO_DATA3_PORT)
+#define IO_CTL1                        REG16PTR(IO_CTL1_PORT)
+#define IO_CTL2                        REG16PTR(IO_CTL2_PORT)
+#define IO_CTL3                        REG16PTR(IO_CTL3_PORT)
+#define IO_TX1                 REG16PTR(IO_TX1_PORT)
+#define IO_RX1                 REG16PTR(IO_RX1_PORT)
+#define IO_SCTL1               REG16PTR(IO_SCTL1_PORT)
+#define IO_TX2                 REG16PTR(IO_TX2_PORT)
+#define IO_RX2                 REG16PTR(IO_RX2_PORT)
+#define IO_SCTL2               REG16PTR(IO_SCTL2_PORT)
+#define IO_TX3                 REG16PTR(IO_TX3_PORT)
+#define IO_RX3                 REG16PTR(IO_RX3_PORT)
+#define IO_SCTL3               REG16PTR(IO_SCTL3_PORT)
+
 #endif /* !def ASM */
 
+
+/* --- VDP registers --- */
+
 #define VDP_REG_MODE1          0
 #define VDP_REG_MODE2          1
 #define VDP_REG_NAMEA          2
@@ -108,4 +144,27 @@
 #define VDP_DMA_FILL   0x80
 #define VDP_DMA_COPY   0xc0
 
+/* --- I/O registers --- */
+
+#define IO_BIT_UP              0x01
+#define IO_BIT_DOWN            0x02
+#define IO_BIT_LEFT            0x04
+#define IO_BIT_RIGHT   0x08
+#define IO_BIT_TL              0x10
+#define IO_BIT_TR              0x20
+#define IO_BIT_TH              0x40
+
+#define IO_CTL_INT             0x80
+
+#define IO_SCTL_TXFULL 0x01
+#define IO_SCTL_RXRDY  0x02
+#define IO_SCTL_RXERR  0x04
+#define IO_SCTL_RXINT  0x08
+#define IO_SCTL_SEROUT 0x10
+#define IO_SCTL_SERIN  0x20
+#define IO_SCTL_B4800  0
+#define IO_SCTL_B2400  0x40
+#define IO_SCTL_B1200  0x80
+#define IO_SCTL_B300   0xc0
+
 #endif /* HWREGS_H_ */