.macro vdp_setreg reg val
- move.w #(\val), %d0
- or.w #(0x8000 + (\reg << 8)), %d0
- move.w %d0, VDP_CTL_PORT
+ move.w #(0x8000 + ((\reg) << 8) + (\val)), VDP_CTL_PORT
.endm
- .macro vdp_setreg_reg reg val
- or.w #(0x8000 + (\reg << 8)), \val
- move.w \val, VDP_CTL_PORT
+ .macro vdp_setreg_reg vdpreg valreg
+ and.w #0xff, \valreg
+ or.w #(0x8000 + ((\vdpreg) << 8)), \valreg
+ move.w \valreg, VDP_CTL_PORT
+ .endm
+
+ .macro vdp_setup_addr type addr
+ move.l #((\type) + (((\addr) & 0x3fff) << 16) + (((\addr) >> 14) & 3)), VDP_CTL_PORT
+ .endm
+
+ .macro vdp_setup_addr_reg type addr
+ lsl.l #2, \addr
+ lsr.w #2, \addr
+ swap \addr
+ or.l #(\type), \addr
+ move.l \addr, VDP_CTL_PORT
.endm
| vi:ft=gas68k: