+#define VDP_DATA REG16PTR(VDP_DATA_PORT)
+#define VDP_CTL REG16PTR(VDP_CTL_PORT)
+#define VDP_CTL32 REG32PTR(VDP_CTL_PORT)
+#define VDP_STAT VDP_CTL
+#endif /* !def ASM */
+
+#define VDP_REG_MODE1 0
+#define VDP_REG_MODE2 1
+#define VDP_REG_NAMEA 2
+#define VDP_REG_NAMEW 3
+#define VDP_REG_NAMEB 4
+#define VDP_REG_SPR 5
+#define VDP_REG_BGCOL 7
+#define VDP_REG_HINTR 10
+#define VDP_REG_MODE3 11
+#define VDP_REG_MODE4 12
+#define VDP_REG_HSCROLL 13
+#define VDP_REG_AUTOINC 15
+#define VDP_REG_SCROLLSZ 16
+#define VDP_REG_WINX 17
+#define VDP_REG_WINY 18
+#define VDP_REG_DMACNTL 19
+#define VDP_REG_DMACNTH 20
+#define VDP_REG_DMASRCL 21
+#define VDP_REG_DMASRCM 22
+#define VDP_REG_DMASRCH 23
+
+#define VDP_ST_PAL 0x001
+#define VDP_ST_DMA 0x002
+#define VDP_ST_HBLANK 0x004
+#define VDP_ST_VBLANK 0x008
+#define VDP_ST_ODDFRM 0x010
+#define VDP_ST_COL 0x020
+#define VDP_ST_SPROVF 0x040
+#define VDP_ST_VINTR 0x080
+#define VDP_ST_FULL 0x100
+#define VDP_ST_EMPT 0x200
+
+#define VDP_M1_INIT 0x04
+#define VDP_M1_HVSTOP 0x02
+#define VDP_M1_HINTR 0x10
+
+#define VDP_M2_INIT 0x04
+#define VDP_M2_V30 0x08
+#define VDP_M2_DMA 0x10
+#define VDP_M2_VINTR 0x20
+#define VDP_M2_DISP 0x40
+
+#define VDP_NA_ADDR(x) (((x) >> 14) & 0x38)
+#define VDP_NW_ADDR(x) (((x) >> 14) & 0x3e)
+#define VDP_NB_ADDR(x) ((x) >> 17)
+#define VDP_SPRTAB_ADDR(x) ((x) >> 9)
+#define VDP_HSTAB_ADDR(x) ((x) >> 10)
+
+#define VDP_BGCOL(pal, col) (((pal) << 4) | (col))
+
+#define VDP_M3_HFULL 0
+#define VDP_M3_HCELL 0x02
+#define VDP_M3_HLINE 0x03
+#define VDP_M3_VFULL 0
+#define VDP_M3_V2CELL 0x04
+#define VDP_M3_EXTINTR 0x08
+
+#define VDP_M4_H40 0x81
+#define VDP_M4_ILACE 0x02
+#define VDP_M4_ILACE2X 0x06
+#define VDP_M4_SHAD 0x08
+
+#define VDP_SCR_H32 0
+#define VDP_SCR_H64 0x01
+#define VDP_SCR_H128 0x03
+#define VDP_SCR_V32 0
+#define VDP_SCR_V64 0x10
+#define VDP_SCR_V128 0x30
+
+#define VDP_WINX_RIGHT 0x80
+#define VDP_WINY_DOWN 0x80
+
+#define VDP_DMA_MEM 0
+#define VDP_DMA_FILL 0x80
+#define VDP_DMA_COPY 0xc0