DMA version of the waving logo

diff --git a/65816.inc b/65816.inc
new file mode 100644 (file)
index 0000000..8997c5f
--- /dev/null
+++ b/65816.inc
@@ -0,0 +1,23 @@
+       .macro A16
+       rep #$20
+       .a16
+       .endmacro
+       .macro A8
+       sep #$20
+       .a8
+       .endmacro
+       .macro I16
+       rep #$10
+       .i16
+       .endmacro
+       .macro I8
+       sep #$10
+       .i8
+       .endmacro
+
+       .macro asr
+       cmp #$80
+       ror a
+       .endmacro
+
+       ; vi:ft=asm_ca65:

diff --git a/hwregs.inc b/hwregs.inc
index 5fd9f2c..92afad8 100644 (file)
--- a/hwregs.inc
+++ b/hwregs.inc
@@ -12,14 +12,14 @@
        REG_BG4SC       = $210a
        REG_BG12NBA     = $210b
        REG_BG34NBA     = $210c
-       REG_BG1HOFFS    = $210d
-       REG_BG1VOFFS    = $210e
-       REG_BG2HOFFS    = $210f
-       REG_BG2VOFFS    = $2110
-       REG_BG3HOFFS    = $2111
-       REG_BG3VOFFS    = $2112
-       REG_BG4HOFFS    = $2113
-       REG_BG4VOFFS    = $2114
+       REG_BG1HOFS     = $210d
+       REG_BG1VOFS     = $210e
+       REG_BG2HOFS     = $210f
+       REG_BG2VOFS     = $2110
+       REG_BG3HOFS     = $2111
+       REG_BG3VOFS     = $2112
+       REG_BG4HOFS     = $2113
+       REG_BG4VOFS     = $2114
        REG_VMAINC      = $2115
        REG_VMADDL      = $2116
        REG_VMADDH      = $2117
@@ -96,17 +96,17 @@
        REG_A2AH_BASE   = $4309
        REG_NTRL_BASE   = $430a
 
-       .define REG_DMAP(n)     (REG_DMAP_BASE | (n << 4))
-       .define REG_BBAD(n)     (REG_BBAD_BASE | (n << 4))
-       .define REG_A1TL(n)     (REG_A1TL_BASE | (n << 4))
-       .define REG_A1TH(n)     (REG_A1TH_BASE | (n << 4))
-       .define REG_A1B(n)      (REG_A1B_BASE | (n << 4))
-       .define REG_DASL(n)     (REG_DASL_BASE | (n << 4))
-       .define REG_DASH(n)     (REG_DASH_BASE | (n << 4))
-       .define REG_DASB(n)     (REG_DASB_BASE | (n << 4))
-       .define REG_A2AL(n)     (REG_A2AL_BASE | (n << 4))
-       .define REG_A2AH(n)     (REG_A2AH_BASE | (n << 4))
-       .define REG_NTRL(n)     (REG_NTRL_BASE | (n << 4))
+       .define REG_DMAP(n)     REG_DMAP_BASE | (n << 4)
+       .define REG_BBAD(n)     REG_BBAD_BASE | (n << 4)
+       .define REG_A1TL(n)     REG_A1TL_BASE | (n << 4)
+       .define REG_A1TH(n)     REG_A1TH_BASE | (n << 4)
+       .define REG_A1B(n)      REG_A1B_BASE | (n << 4)
+       .define REG_DASL(n)     REG_DASL_BASE | (n << 4)
+       .define REG_DASH(n)     REG_DASH_BASE | (n << 4)
+       .define REG_DASB(n)     REG_DASB_BASE | (n << 4)
+       .define REG_A2AL(n)     REG_A2AL_BASE | (n << 4)
+       .define REG_A2AH(n)     REG_A2AH_BASE | (n << 4)
+       .define REG_NTRL(n)     REG_NTRL_BASE | (n << 4)
 
 
        .macro setreg reg, val

diff --git a/test.asm b/test.asm
index 4c51874..da5f5ec 100644 (file)
--- a/test.asm
+++ b/test.asm
@@ -1,4 +1,5 @@
        .p816
+       .include "65816.inc"
        .include "hwregs.inc"
 
        .segment "rodata"
@@ -7,23 +8,6 @@
 
        .segment "code"
 
-       .macro A16
-       rep #$20
-       .a16
-       .endmacro
-       .macro A8
-       sep #$20
-       .a8
-       .endmacro
-       .macro I16
-       rep #$10
-       .i16
-       .endmacro
-       .macro I8
-       sep #$10
-       .i8
-       .endmacro
-
        ; VMEM map
        ; 0000: tilemap for BG1 (32x32 4bpp: 512b)
        ; 2048: BG3-base (h/v offsets)
@@ -36,12 +20,10 @@
        clc
        xce
 
-       rep #$10
-       .i16
+       I16
        ldx #$1fff
        txs
-       sep #$10
-       .i8
+       I8
 
        jsr snes_init
        setreg REG_SETINI, $4   ; 239 lines
@@ -90,14 +72,12 @@ cmap_loop:
        nframe = 0
        ncol = 2
        anim = 4
+       vscroll = 8
+       shadow_voffs = 32
 
        A16
        stz nframe
-       A8
 mainloop:
-       wait_vblank
-
-       A16
        lda nframe
        lsr
        lsr
@@ -105,11 +85,6 @@ mainloop:
        inc nframe
        A8
 
-       lda #(vmem_voffs_offs & $ff)
-       sta REG_VMADDL
-       lda #(vmem_voffs_offs >> 8)
-       sta REG_VMADDH
-
        stz ncol
 @cloop:
        lda anim
@@ -118,29 +93,62 @@ mainloop:
        asl
        tax
        lda sintab,x
-       lsr
-       lsr
-       lsr
+       sec
+       sbc #128
+       asr
+       asr
+       asr
 
        ldx ncol
        bne @per_tile_offs
        ; global scroll for the first column
-       sta REG_BG1VOFFS
-       stz REG_BG1VOFFS
+       ;sta REG_BG1VOFS
+       sta vscroll
+       ;stz REG_BG1VOFS
        bra @end
 
 @per_tile_offs:
-       sta REG_VMDATAL
-       lda #$20        ; enable for BG1
-       sta REG_VMDATAH
+       pha
+       lda ncol
+       asl
+       tax     ; x = ncol << 1
+       pla
+       ;sta REG_VMDATAL
+       ;lda #$20       ; enable for BG1
+       ;sta REG_VMDATAH
+       sta shadow_voffs,x
+       inx
+       lda #$20
+       sta shadow_voffs,x
 @end:
-
        inc ncol
        lda ncol
        and #$1f
        bne @cloop
 
-       bra mainloop
+       ; wait for vblank, and DMA the table to vmem
+       wait_vblank
+       fblank 1
+       lda vscroll
+       sta REG_BG1VOFS
+       stz REG_BG1VOFS
+       lda #(vmem_voffs_offs & $ff)
+       sta REG_VMADDL
+       lda #(vmem_voffs_offs >> 8)
+       sta REG_VMADDH
+       setreg REG_MDMAEN, 0
+       setreg REG_DMAP(0), $01                 ; A->B words at X,X+1, A inc
+       setreg REG_BBAD(0), REG_VMDATAL & $ff   ; write to VMDATAL,VMDATAH
+       setreg REG_A1TL(0), shadow_voffs
+       setreg REG_A1TH(0), 0
+       setreg REG_A1B(0), 0
+       setreg REG_DASL(0), 64
+       setreg REG_DASH(0), 0
+       setreg REG_DASB(0), 0
+       setreg REG_MDMAEN, 1                    ; enable DMA channel 0
+       fblank 0
+       A16
+       jmp mainloop
 
        ; copy_vmem(vmem_offset, src, num_words)
 copy_vmem:
@@ -150,8 +158,7 @@ copy_vmem:
        phd             ; save d
        tsc             ; and make it point to the stack
        tcd
-       sep #$20        ; restore 8bit accum
-       .a8
+       A8      ; restore 8bit accum
        ; stack frame
        ; $1 saved D
        ; $3 return address
@@ -177,8 +184,7 @@ copy_vmem:
        bne @loop
        
        pld
-       sep #$10        ; back to 8bit index registers
-       .i8
+       I8              ; back to 8bit index registers
        rts
 
 
@@ -197,22 +203,22 @@ snes_init:
        stz REG_BG4SC
        stz REG_BG12NBA
        stz REG_BG34NBA
-       stz REG_BG1HOFFS
-       stz REG_BG1HOFFS
-       stz REG_BG1VOFFS
-       stz REG_BG1VOFFS
-       stz REG_BG2HOFFS
-       stz REG_BG2HOFFS
-       stz REG_BG2VOFFS
-       stz REG_BG2VOFFS
-       stz REG_BG3HOFFS
-       stz REG_BG3HOFFS
-       stz REG_BG3VOFFS
-       stz REG_BG3VOFFS
-       stz REG_BG4HOFFS
-       stz REG_BG4HOFFS
-       stz REG_BG4VOFFS
-       stz REG_BG4VOFFS
+       stz REG_BG1HOFS
+       stz REG_BG1HOFS
+       stz REG_BG1VOFS
+       stz REG_BG1VOFS
+       stz REG_BG2HOFS
+       stz REG_BG2HOFS
+       stz REG_BG2VOFS
+       stz REG_BG2VOFS
+       stz REG_BG3HOFS
+       stz REG_BG3HOFS
+       stz REG_BG3VOFS
+       stz REG_BG3VOFS
+       stz REG_BG4HOFS
+       stz REG_BG4HOFS
+       stz REG_BG4VOFS
+       stz REG_BG4VOFS
        setreg REG_VMAINC, $80
        stz REG_VMADDL
        stz REG_VMADDH