#include <conio.h>\r
#include "dma.h"\r
\r
-/* 8bit DMA ports */\r
-#define DMA_0_ADDR 0x00\r
-#define DMA_0_COUNT 0x01\r
-#define DMA_1_ADDR 0x02\r
-#define DMA_1_COUNT 0x03\r
-#define DMA_2_ADDR 0x04\r
-#define DMA_2_COUNT 0x05\r
-#define DMA_3_ADDR 0x06\r
-#define DMA_3_COUNT 0x07\r
-/* 16bit DMA ports */\r
-#define DMA_4_ADDR 0xc0\r
-#define DMA_4_COUNT 0xc2\r
-#define DMA_5_ADDR 0xc4\r
-#define DMA_5_COUNT 0xc6\r
-#define DMA_6_ADDR 0xc8\r
-#define DMA_6_COUNT 0xca\r
-#define DMA_7_ADDR 0xcc\r
-#define DMA_7_COUNT 0xce\r
-\r
-#define DMA_ADDR(c) \\r
- ((c < 4) ? DMA_0_ADDR + ((c) << 1) : (DMA_4_ADDR + ((c) << 2)))\r
-#define DMA_COUNT(c) \\r
- ((c < 4) ? DMA_0_COUNT + ((c) << 1) : (DMA_4_COUNT + ((c) << 2)))\r
-\r
-#define DMA8_MASK 0x0a\r
-#define DMA8_MODE 0x0b\r
-#define DMA8_CLR_FLIPFLOP 0x0c\r
-#define DMA8_RESET 0x0d\r
-#define DMA8_MASK_RST 0x0e\r
-#define DMA8_RMASK 0x0f\r
-#define DMA16_MASK 0xd4\r
-#define DMA16_MODE 0xd6\r
-#define DMA16_CLR_FLIPFLOP 0xd8\r
-#define DMA16_RESET 0xda\r
-#define DMA16_MASK_RST 0xdc\r
-#define DMA16_RMASK 0xde\r
-\r
-#define DMA_MASK(c) ((c) < 4 ? DMA8_MASK : DMA16_MASK)\r
-#define DMA_MODE(c) ((c) < 4 ? DMA8_MODE : DMA16_MODE)\r
-#define DMA_CLR_FLIPFLOP(c) ((c) < 4 ? DMA8_CLR_FLIPFLOP : DMA16_CLR_FLIPFLOP)\r
-#define DMA_RESET(c) ((c) < 4 ? DMA8_RESET : DMA16_RESET)\r
-#define DMA_MASK_RST(c) ((c) < 4 ? DMA8_MASK_RST : DMA16_MASK_RST)\r
-#define DMA_RMASK(c) ((c) < 4 ? DMA8_RMASK : DMA16_RMASK)\r
-\r
-#define DMA_0_PAGE 0x87\r
-#define DMA_1_PAGE 0x83\r
-#define DMA_2_PAGE 0x81\r
-#define DMA_3_PAGE 0x82\r
-#define DMA_4_PAGE 0x8f\r
-#define DMA_5_PAGE 0x8b\r
-#define DMA_6_PAGE 0x89\r
-#define DMA_7_PAGE 0x8a\r
-\r
#define MODE_CHAN(x) ((x) & 3)\r
#define MODE_WRITE 0x04\r
#define MODE_READ 0x08\r
static __inline void mask(int chan);\r
static __inline void unmask(int chan);\r
\r
-static int page_port[] = {\r
- DMA_0_PAGE, DMA_1_PAGE, DMA_2_PAGE, DMA_3_PAGE,\r
- DMA_4_PAGE, DMA_5_PAGE, DMA_6_PAGE, DMA_7_PAGE\r
-};\r
+/* DMA register I/O ports for all channels */\r
+static const int addr_port[] = { 0x00, 0x02, 0x04, 0x06, 0xc0, 0xc4, 0xc8, 0xcc };\r
+static const int count_port[] = { 0x01, 0x03, 0x05, 0x07, 0xc2, 0xc6, 0xca, 0xce };\r
+static const int page_port[] = { 0x87, 0x83, 0x81, 0x82, 0x8f, 0x8b, 0x89, 0x8a };\r
+static const int mask_port[] = { 0x0a, 0x0a, 0x0a, 0x0a, 0xd4, 0xd4, 0xd4, 0xd4 };\r
+static const int mode_port[] = { 0x0b, 0x0b, 0x0b, 0x0b, 0xd6, 0xd6, 0xd6, 0xd6 };\r
+static const int clrff_port[] = { 0x0c, 0x0c, 0x0c, 0x0c, 0xd8, 0xd8, 0xd8, 0xd8 };\r
\r
void dma_out(int chan, uint32_t phyaddr, int size, unsigned int flags)\r
{\r
static void dma_io(int chan, uint32_t phyaddr, int size, unsigned int flags, unsigned int dir)\r
{\r
unsigned int mode;\r
- int addr_port, count_port;\r
-\r
- addr_port = DMA_ADDR(chan);\r
- count_port = DMA_COUNT(chan);\r
\r
mask(chan);\r
- outp(DMA_CLR_FLIPFLOP(chan), 0);\r
+ outp(clrff_port[chan], 0);\r
\r
/* first 2 bits of flags correspond to the mode bits 6,7 */\r
mode = ((flags & 3) << 6) | dir | MODE_CHAN(chan);\r
if(flags & DMA_DECR) mode |= MODE_DECR;\r
if(flags & DMA_AUTO) mode |= MODE_AUTO;\r
- outp(DMA_MODE(chan), mode);\r
+ outp(mode_port[chan], mode);\r
\r
if(IS_16BIT(chan)) {\r
phyaddr >>= 1;\r
size >>= 1;\r
}\r
\r
- outp(addr_port, phyaddr & 0xff);\r
- outp(addr_port, (phyaddr >> 8) & 0xff);\r
+ outp(addr_port[chan], phyaddr & 0xff);\r
+ outp(addr_port[chan], (phyaddr >> 8) & 0xff);\r
outp(page_port[chan], (phyaddr >> 16) & 0xff);\r
\r
size--;\r
- outp(count_port, size & 0xff);\r
- outp(count_port, (size >> 8) & 0xff);\r
+ outp(count_port[chan], size & 0xff);\r
+ outp(count_port[chan], (size >> 8) & 0xff);\r
\r
unmask(chan);\r
}\r
\r
static __inline void mask(int chan)\r
{\r
- outp(DMA_MASK(chan), MASK_CHAN(chan) | MASK_DISABLE);\r
+ outp(mask_port[chan], MASK_CHAN(chan) | MASK_DISABLE);\r
}\r
\r
static __inline void unmask(int chan)\r
{\r
- outp(DMA_MASK(chan), MASK_CHAN(chan));\r
+ outp(mask_port[chan], MASK_CHAN(chan));\r
}\r