From: John Tsiombikas Date: Wed, 27 Dec 2023 03:16:28 +0000 (+0200) Subject: input handling X-Git-Url: http://git.mutantstargoat.com/user/nuclear/?a=commitdiff_plain;h=4ecfbbd039d4a74f3cdaf92abf5387e782030fc5;p=mdlife input handling --- diff --git a/src/debug.h b/src/debug.h index 0bf525d..491b288 100644 --- a/src/debug.h +++ b/src/debug.h @@ -1,6 +1,10 @@ #ifndef DEBUG_H_ #define DEBUG_H_ +#include + +extern uint32_t dbgval[]; + void dbg_init(void); void dbg_printchar(int x, int y, char c); diff --git a/src/demo.h b/src/demo.h index b72b158..24e4733 100644 --- a/src/demo.h +++ b/src/demo.h @@ -4,6 +4,7 @@ #include extern uint32_t frameno; +extern uint16_t bnstate; void dna_init(void); void dna_update(void); diff --git a/src/hwregs.h b/src/hwregs.h index 2838026..8e21f25 100644 --- a/src/hwregs.h +++ b/src/hwregs.h @@ -4,6 +4,22 @@ #define VDP_DATA_PORT 0xc00000 #define VDP_CTL_PORT 0xc00004 +#define IO_DATA1_PORT 0xa10003 +#define IO_DATA2_PORT 0xa10005 +#define IO_DATA3_PORT 0xa10007 +#define IO_CTL1_PORT 0xa10009 +#define IO_CTL2_PORT 0xa1000b +#define IO_CTL3_PORT 0xa1000d +#define IO_TX1_PORT 0xa1000f +#define IO_RX1_PORT 0xa10011 +#define IO_SCTL1_PORT 0xa10013 +#define IO_TX2_PORT 0xa10015 +#define IO_RX2_PORT 0xa10017 +#define IO_SCTL2_PORT 0xa10019 +#define IO_TX3_PORT 0xa1001b +#define IO_RX3_PORT 0xa1001d +#define IO_SCTL3_PORT 0xa1001f + /* VDP access type */ #define VDP_VRAM 0x40000000 #define VDP_CRAM 0xc0000000 @@ -28,8 +44,28 @@ #define VDP_CTL REG16PTR(VDP_CTL_PORT) #define VDP_CTL32 REG32PTR(VDP_CTL_PORT) #define VDP_STAT VDP_CTL + +#define IO_DATA1 REG16PTR(IO_DATA1_PORT) +#define IO_DATA2 REG16PTR(IO_DATA2_PORT) +#define IO_DATA3 REG16PTR(IO_DATA3_PORT) +#define IO_CTL1 REG16PTR(IO_CTL1_PORT) +#define IO_CTL2 REG16PTR(IO_CTL2_PORT) +#define IO_CTL3 REG16PTR(IO_CTL3_PORT) +#define IO_TX1 REG16PTR(IO_TX1_PORT) +#define IO_RX1 REG16PTR(IO_RX1_PORT) +#define IO_SCTL1 REG16PTR(IO_SCTL1_PORT) +#define IO_TX2 REG16PTR(IO_TX2_PORT) +#define IO_RX2 REG16PTR(IO_RX2_PORT) +#define IO_SCTL2 REG16PTR(IO_SCTL2_PORT) +#define IO_TX3 REG16PTR(IO_TX3_PORT) +#define IO_RX3 REG16PTR(IO_RX3_PORT) +#define IO_SCTL3 REG16PTR(IO_SCTL3_PORT) + #endif /* !def ASM */ + +/* --- VDP registers --- */ + #define VDP_REG_MODE1 0 #define VDP_REG_MODE2 1 #define VDP_REG_NAMEA 2 @@ -108,4 +144,27 @@ #define VDP_DMA_FILL 0x80 #define VDP_DMA_COPY 0xc0 +/* --- I/O registers --- */ + +#define IO_BIT_UP 0x01 +#define IO_BIT_DOWN 0x02 +#define IO_BIT_LEFT 0x04 +#define IO_BIT_RIGHT 0x08 +#define IO_BIT_TL 0x10 +#define IO_BIT_TR 0x20 +#define IO_BIT_TH 0x40 + +#define IO_CTL_INT 0x80 + +#define IO_SCTL_TXFULL 0x01 +#define IO_SCTL_RXRDY 0x02 +#define IO_SCTL_RXERR 0x04 +#define IO_SCTL_RXINT 0x08 +#define IO_SCTL_SEROUT 0x10 +#define IO_SCTL_SERIN 0x20 +#define IO_SCTL_B4800 0 +#define IO_SCTL_B2400 0x40 +#define IO_SCTL_B1200 0x80 +#define IO_SCTL_B300 0xc0 + #endif /* HWREGS_H_ */ diff --git a/src/main.c b/src/main.c index 261f1a5..672e4de 100644 --- a/src/main.c +++ b/src/main.c @@ -1,6 +1,7 @@ #include #include "z80.h" #include "vdp.h" +#include "pad.h" #include "sprite.h" #include "parts.h" #include "debug.h" @@ -11,9 +12,11 @@ uint32_t dbgval[4]; int main(void) { int i; + static unsigned short bnprev; z80_init(); vdp_init(); + pad_init(); dbg_init(); dna_init(); @@ -32,6 +35,9 @@ int main(void) vdp_wait_vblank(); spr_submit(); + bnstate = pad_read(0); + bndiff = bnstate ^ bnprev; + bnprev = bnstate; frameno++; } diff --git a/src/pad.S b/src/pad.S new file mode 100644 index 0000000..11e3828 --- /dev/null +++ b/src/pad.S @@ -0,0 +1,45 @@ + .text + +#include "hwregs.h" + .include "z80.inc" + + .globl pad_init +pad_init: + move.b #IO_BIT_TH, %d0 + move.b %d0, IO_CTL1_PORT + move.b %d0, IO_DATA1_PORT + move.b %d0, IO_CTL2_PORT + move.b %d0, IO_DATA2_PORT + move.b %d0, IO_CTL3_PORT + move.b %d0, IO_DATA3_PORT + rts + + .globl pad_read +pad_read: + | Z80 busreq to avoid messing up its wait states (bulletin #4) + z80_grab_wait + move.l 4(%sp), %d0 + lsl.l #1, %d0 + add.l #IO_DATA1_PORT, %d0 + move.l %d0, %a0 + move.b #IO_BIT_TH, (%a0) + clr.l %d0 + nop + move.b (%a0), %d0 + move.b #0, (%a0) + and.b #0x3f, %d0 + move.b (%a0), %d1 + lsl.b #2, %d1 + and.b #0xc0, %d1 + or.b %d1, %d0 + not.b %d0 + z80_release + rts + + .bss + .globl bnstate + .globl bndiff +bnstate: .word 0 +bndiff: .word 0 + +| vi:ft=gas68k: diff --git a/src/pad.h b/src/pad.h new file mode 100644 index 0000000..ebb6944 --- /dev/null +++ b/src/pad.h @@ -0,0 +1,18 @@ +#ifndef PAD_H_ +#define PAD_H_ + +#define PAD_UP 0x0001 +#define PAD_DOWN 0x0002 +#define PAD_LEFT 0x0004 +#define PAD_RIGHT 0x0008 +#define PAD_B 0x0010 +#define PAD_C 0x0020 +#define PAD_A 0x0040 +#define PAD_START 0x0080 + +extern unsigned short bnstate, bndiff; + +void pad_init(void); +unsigned short pad_read(int port); + +#endif /* PAD_H_ */ diff --git a/src/part_dna.c b/src/part_dna.c index da0d5a0..d5edadb 100644 --- a/src/part_dna.c +++ b/src/part_dna.c @@ -1,7 +1,9 @@ #include "sprite.h" #include "vdp.h" #include "demo.h" +#include "pad.h" #include "parts.h" +#include "debug.h" static void particle(int x, int y, int sz); @@ -33,36 +35,82 @@ void dna_init(void) void dna_update(void) { - particle(160, 120, frameno & 0x1f); + static int x = 160; + static int y = 120; + static int sz = 0; + + if(bnstate & PAD_UP) { + if(y > 0) y--; + } else if(bnstate & PAD_DOWN) { + if(y < 239) y++; + } + if(bnstate & PAD_LEFT) { + if(y > 0) x--; + } else if(bnstate & PAD_RIGHT) { + if(y < 319) x++; + } + if(bndiff & bnstate & PAD_A) { + if(sz > 0) sz--; + } else if(bndiff & bnstate & PAD_B) { + if(sz < 32) sz++; + } + + particle(x, y, sz); } -static void particle(int x, int y, int sz) +static void particle(int x, int y, int pixsz) { - int tile; + int tile, offs = 4, szlevel; - sz >>= 3; /* pixels to levels */ - if(sz > 4) sz = 4; - tile = VDP_ADDR2TILE(SPRITE_BASE) + sz; + if(pixsz < 2) { + szlevel = 0; + pixsz = 2; + tile = VDP_ADDR2TILE(SPRITE_BASE); + } else if(pixsz < 16) { + szlevel = pixsz >> 1; + tile = VDP_ADDR2TILE(SPRITE_BASE) + szlevel; + } else if(pixsz < 24) { + szlevel = 7; + tile = VDP_ADDR2TILE(SPRITE_BASE) + szlevel; + } else if(pixsz < 32) { + szlevel = 8; + } else { + szlevel = 9; + pixsz = 32; + } - switch(sz) { + dbgval[0] = pixsz; + dbgval[1] = szlevel; + + tile = VDP_ADDR2TILE(SPRITE_BASE) + (pixsz < 32 ? szlevel : 12); + + switch(szlevel) { case 0: case 1: case 2: + case 3: spr_add(x - 4, y - 4, VDP_TILENAME(tile, 1, VDP_TILE_FG), SPR_SIZE(1, 1)); break; - case 3: - spr_add(x - 8, y - 8, VDP_TILENAME(tile, 1, VDP_TILE_FG), SPR_SIZE(1, 1)); - spr_add(x, y - 8, VDP_TILENAME(tile, 1, VDP_TILE_FG | VDP_TILE_HFLIP), SPR_SIZE(1, 1)); - spr_add(x - 8, y, VDP_TILENAME(tile, 1, VDP_TILE_FG | VDP_TILE_VFLIP), SPR_SIZE(1, 1)); + case 4: /* 10x10 */ + case 5: /* 12x12 */ + case 6: /* 14x14 */ + case 7: /* 16x16 */ + offs = 8; + spr_add(x - offs, y - offs, VDP_TILENAME(tile, 1, VDP_TILE_FG), SPR_SIZE(1, 1)); + spr_add(x, y - offs, VDP_TILENAME(tile, 1, VDP_TILE_FG | VDP_TILE_HFLIP), SPR_SIZE(1, 1)); + spr_add(x - offs, y, VDP_TILENAME(tile, 1, VDP_TILE_FG | VDP_TILE_VFLIP), SPR_SIZE(1, 1)); spr_add(x, y, VDP_TILENAME(tile, 1, VDP_TILE_FG | VDP_TILE_HVFLIP), SPR_SIZE(1, 1)); break; - case 4: - spr_add(x - 16, y - 16, VDP_TILENAME(tile, 1, VDP_TILE_FG), SPR_SIZE(2, 2)); - spr_add(x, y - 16, VDP_TILENAME(tile, 1, VDP_TILE_FG | VDP_TILE_HFLIP), SPR_SIZE(2, 2)); - spr_add(x - 16, y, VDP_TILENAME(tile, 1, VDP_TILE_FG | VDP_TILE_VFLIP), SPR_SIZE(2, 2)); + default: + offs = 8 + (pixsz & 7); + spr_add(x - offs, y - offs, VDP_TILENAME(tile, 1, VDP_TILE_FG), SPR_SIZE(2, 2)); + spr_add(x, y - offs, VDP_TILENAME(tile, 1, VDP_TILE_FG | VDP_TILE_HFLIP), SPR_SIZE(2, 2)); + spr_add(x - offs, y, VDP_TILENAME(tile, 1, VDP_TILE_FG | VDP_TILE_VFLIP), SPR_SIZE(2, 2)); spr_add(x, y, VDP_TILENAME(tile, 1, VDP_TILE_FG | VDP_TILE_HVFLIP), SPR_SIZE(2, 2)); break; } + + dbgval[2] = offs; } diff --git a/src/z80.inc b/src/z80.inc new file mode 100644 index 0000000..0344ebe --- /dev/null +++ b/src/z80.inc @@ -0,0 +1,22 @@ + .equ Z80_MEMMODE, 0xa11000 + .equ Z80_BUSREQ, 0xa11100 + .equ Z80_RESET, 0xa11200 + .equ Z80_MEM, 0xa00000 + + .macro z80_grab + move.w #0x100, Z80_BUSREQ + .endm + + .macro z80_grab_wait + move.w #0x100, Z80_BUSREQ +wait_z80_\@: + btst #0, Z80_BUSREQ + bne.s wait_z80_\@ + .endm + + .macro z80_release + move.w #0, Z80_BUSREQ + .endm + + +| vi:ft=gas68k: