--- /dev/null
+; interrupt entry routines
+ cpu 8086
+ bits 16
+ section .text
+
+extern dispatch_intr
+
+%macro INTR_ENTRY 2
+global intr_entry_%2
+intr_entry_%2:
+ push bp
+ push ax
+ push bp
+ mov bp, sp
+ mov ax, %1
+ mov [bp + 4], ax
+ pop bp
+ pop ax
+ jmp intr_entry_common
+%endmacro
+
+intr_entry_common:
+ push ax
+ mov ax, sp
+ add ax, 2
+ push cx
+ push dx
+ push bx
+ push ax ; saved sp
+ push bp
+ push si
+ push di
+ call dispatch_intr
+ pop di
+ pop si
+ pop bp
+ pop bx ; throw away saved sp
+ pop bx
+ pop dx
+ pop cx
+ pop ax
+ add sp, 2 ; remove interrupt number from the stack
+ iret
+
+; CPU exceptions
+INTR_ENTRY 0, div
+INTR_ENTRY 1, trap
+INTR_ENTRY 2, nmi
+INTR_ENTRY 3, break
+INTR_ENTRY 4, ovf
+INTR_ENTRY 5, bound
+INTR_ENTRY 6, ill
+; IRQs
+INTR_ENTRY 8, irq0
+INTR_ENTRY 9, irq1
+INTR_ENTRY 10, irq2
+INTR_ENTRY 11, irq3
+INTR_ENTRY 12, irq4
+INTR_ENTRY 13, irq5
+INTR_ENTRY 14, irq6
+INTR_ENTRY 15, irq7
+
+; vi:ts=8 sts=8 sw=8 ft=nasm: