1 ; vi:filetype=nasm ts=8 sts=8 sw=8:
10 GATE_PRESENT equ 8000h
25 cmp ebx, 32 ; determine if it's an IRQ or an exception (trap)
30 lea ebx, [ebx * 8 + idt] ; ebx <- pointer to gate descriptor
31 ; type|dpl goes to the 3rd dword of the descriptor (dpl is 0)
32 or eax, (GATE_DEFAULT | GATE_PRESENT)
34 ; address low 16bits go to the first dword of the descriptor
37 ; address high 16bits go to the last dword of the descriptor
40 ; selector (kcode:1) goes to the second dword of the descriptor
41 mov dword [ebx + 4], 08h
43 ; install dummy interrupt handlers for all IRQ vectors
46 set_irq_vector i, dummy_intr_pic1
47 set_irq_vector i+8, dummy_intr_pic2
67 ; PIC initialization command word 1 bits
68 ICW1_ICW4_NEEDED equ 01h
70 ICW1_INTERVAL4 equ 04h
73 ; PIC initialization command word 4 bits
76 ICW4_BUF_SLAVE equ 08h
77 ICW4_BUF_MASTER equ 0ch
81 ; send ICW1 saying we'll follow with ICW4 later on
82 mov al, ICW1_INIT | ICW1_ICW4_NEEDED
85 ; send ICW2 with IRQ remapping
90 ; send ICW3 to setup the master/slave relationship
91 ; ... set bit3 = 3rd interrupt input has a slave
94 ; ... set slave ID to 2
97 ; send ICW4 to set 8086 mode (no calls generated)
101 ; done, reset the data port to 0