git.mutantstargoat.com Git - nixiedisp/blob - hw/nixiedisp.pro

   1 update=Fri 25 Dec 2020 03:53:10 PM EET
   2 version=1
   3 last_client=kicad
   4 [general]
   5 version=1
   6 RootSch=
   7 BoardNm=
   8 [cvpcb]
   9 version=1
  10 NetIExt=net
  11 [eeschema]
  12 version=1
  13 LibDir=
  14 [eeschema/libraries]
  15 [schematic_editor]
  16 version=1
  17 PageLayoutDescrFile=
  18 PlotDirectoryName=
  19 SubpartIdSeparator=0
  20 SubpartFirstId=65
  21 NetFmtName=Pcbnew
  22 SpiceAjustPassiveValues=0
  23 LabSize=50
  24 ERC_TestSimilarLabels=1
  25 [pcbnew]
  26 version=1
  27 PageLayoutDescrFile=
  28 LastNetListRead=nixiedisp.net
  29 CopperLayerCount=2
  30 BoardThickness=1.6
  31 AllowMicroVias=0
  32 AllowBlindVias=0
  33 RequireCourtyardDefinitions=0
  34 ProhibitOverlappingCourtyards=1
  35 MinTrackWidth=0.2
  36 MinViaDiameter=0.4
  37 MinViaDrill=0.3
  38 MinMicroViaDiameter=0.2
  39 MinMicroViaDrill=0.09999999999999999
  40 MinHoleToHole=0.25
  41 TrackWidth1=0.25
  42 ViaDiameter1=0.8
  43 ViaDrill1=0.4
  44 dPairWidth1=0.2
  45 dPairGap1=0.25
  46 dPairViaGap1=0.25
  47 SilkLineWidth=0.12
  48 SilkTextSizeV=1
  49 SilkTextSizeH=1
  50 SilkTextSizeThickness=0.15
  51 SilkTextItalic=0
  52 SilkTextUpright=1
  53 CopperLineWidth=0.2
  54 CopperTextSizeV=1.5
  55 CopperTextSizeH=1.5
  56 CopperTextThickness=0.3
  57 CopperTextItalic=0
  58 CopperTextUpright=1
  59 EdgeCutLineWidth=0.05
  60 CourtyardLineWidth=0.05
  61 OthersLineWidth=0.15
  62 OthersTextSizeV=1
  63 OthersTextSizeH=1
  64 OthersTextSizeThickness=0.15
  65 OthersTextItalic=0
  66 OthersTextUpright=1
  67 SolderMaskClearance=0
  68 SolderMaskMinWidth=0
  69 SolderPasteClearance=0
  70 SolderPasteRatio=-0
  71 [pcbnew/Layer.F.Cu]
  72 Name=F.Cu
  73 Type=0
  74 Enabled=1
  75 [pcbnew/Layer.In1.Cu]
  76 Name=In1.Cu
  77 Type=0
  78 Enabled=0
  79 [pcbnew/Layer.In2.Cu]
  80 Name=In2.Cu
  81 Type=0
  82 Enabled=0
  83 [pcbnew/Layer.In3.Cu]
  84 Name=In3.Cu
  85 Type=0
  86 Enabled=0
  87 [pcbnew/Layer.In4.Cu]
  88 Name=In4.Cu
  89 Type=0
  90 Enabled=0
  91 [pcbnew/Layer.In5.Cu]
  92 Name=In5.Cu
  93 Type=0
  94 Enabled=0
  95 [pcbnew/Layer.In6.Cu]
  96 Name=In6.Cu
  97 Type=0
  98 Enabled=0
  99 [pcbnew/Layer.In7.Cu]
 100 Name=In7.Cu
 101 Type=0
 102 Enabled=0
 103 [pcbnew/Layer.In8.Cu]
 104 Name=In8.Cu
 105 Type=0
 106 Enabled=0
 107 [pcbnew/Layer.In9.Cu]
 108 Name=In9.Cu
 109 Type=0
 110 Enabled=0
 111 [pcbnew/Layer.In10.Cu]
 112 Name=In10.Cu
 113 Type=0
 114 Enabled=0
 115 [pcbnew/Layer.In11.Cu]
 116 Name=In11.Cu
 117 Type=0
 118 Enabled=0
 119 [pcbnew/Layer.In12.Cu]
 120 Name=In12.Cu
 121 Type=0
 122 Enabled=0
 123 [pcbnew/Layer.In13.Cu]
 124 Name=In13.Cu
 125 Type=0
 126 Enabled=0
 127 [pcbnew/Layer.In14.Cu]
 128 Name=In14.Cu
 129 Type=0
 130 Enabled=0
 131 [pcbnew/Layer.In15.Cu]
 132 Name=In15.Cu
 133 Type=0
 134 Enabled=0
 135 [pcbnew/Layer.In16.Cu]
 136 Name=In16.Cu
 137 Type=0
 138 Enabled=0
 139 [pcbnew/Layer.In17.Cu]
 140 Name=In17.Cu
 141 Type=0
 142 Enabled=0
 143 [pcbnew/Layer.In18.Cu]
 144 Name=In18.Cu
 145 Type=0
 146 Enabled=0
 147 [pcbnew/Layer.In19.Cu]
 148 Name=In19.Cu
 149 Type=0
 150 Enabled=0
 151 [pcbnew/Layer.In20.Cu]
 152 Name=In20.Cu
 153 Type=0
 154 Enabled=0
 155 [pcbnew/Layer.In21.Cu]
 156 Name=In21.Cu
 157 Type=0
 158 Enabled=0
 159 [pcbnew/Layer.In22.Cu]
 160 Name=In22.Cu
 161 Type=0
 162 Enabled=0
 163 [pcbnew/Layer.In23.Cu]
 164 Name=In23.Cu
 165 Type=0
 166 Enabled=0
 167 [pcbnew/Layer.In24.Cu]
 168 Name=In24.Cu
 169 Type=0
 170 Enabled=0
 171 [pcbnew/Layer.In25.Cu]
 172 Name=In25.Cu
 173 Type=0
 174 Enabled=0
 175 [pcbnew/Layer.In26.Cu]
 176 Name=In26.Cu
 177 Type=0
 178 Enabled=0
 179 [pcbnew/Layer.In27.Cu]
 180 Name=In27.Cu
 181 Type=0
 182 Enabled=0
 183 [pcbnew/Layer.In28.Cu]
 184 Name=In28.Cu
 185 Type=0
 186 Enabled=0
 187 [pcbnew/Layer.In29.Cu]
 188 Name=In29.Cu
 189 Type=0
 190 Enabled=0
 191 [pcbnew/Layer.In30.Cu]
 192 Name=In30.Cu
 193 Type=0
 194 Enabled=0
 195 [pcbnew/Layer.B.Cu]
 196 Name=B.Cu
 197 Type=0
 198 Enabled=1
 199 [pcbnew/Layer.B.Adhes]
 200 Enabled=1
 201 [pcbnew/Layer.F.Adhes]
 202 Enabled=1
 203 [pcbnew/Layer.B.Paste]
 204 Enabled=1
 205 [pcbnew/Layer.F.Paste]
 206 Enabled=1
 207 [pcbnew/Layer.B.SilkS]
 208 Enabled=1
 209 [pcbnew/Layer.F.SilkS]
 210 Enabled=1
 211 [pcbnew/Layer.B.Mask]
 212 Enabled=1
 213 [pcbnew/Layer.F.Mask]
 214 Enabled=1
 215 [pcbnew/Layer.Dwgs.User]
 216 Enabled=1
 217 [pcbnew/Layer.Cmts.User]
 218 Enabled=1
 219 [pcbnew/Layer.Eco1.User]
 220 Enabled=1
 221 [pcbnew/Layer.Eco2.User]
 222 Enabled=1
 223 [pcbnew/Layer.Edge.Cuts]
 224 Enabled=1
 225 [pcbnew/Layer.Margin]
 226 Enabled=1
 227 [pcbnew/Layer.B.CrtYd]
 228 Enabled=1
 229 [pcbnew/Layer.F.CrtYd]
 230 Enabled=1
 231 [pcbnew/Layer.B.Fab]
 232 Enabled=1
 233 [pcbnew/Layer.F.Fab]
 234 Enabled=1
 235 [pcbnew/Layer.Rescue]
 236 Enabled=0
 237 [pcbnew/Netclasses]
 238 [pcbnew/Netclasses/Default]
 239 Name=Default
 240 Clearance=0.2
 241 TrackWidth=0.25
 242 ViaDiameter=0.8
 243 ViaDrill=0.4
 244 uViaDiameter=0.3
 245 uViaDrill=0.1
 246 dPairWidth=0.2
 247 dPairGap=0.25
 248 dPairViaGap=0.25
 249 [pcbnew/Netclasses/1]
 250 Name=hvpow
 251 Clearance=0.5
 252 TrackWidth=0.35
 253 ViaDiameter=1
 254 ViaDrill=0.6
 255 uViaDiameter=0.3
 256 uViaDrill=0.1
 257 dPairWidth=0.2
 258 dPairGap=0.25
 259 dPairViaGap=0.25
 260 [pcbnew/Netclasses/2]
 261 Name=power
 262 Clearance=0.2
 263 TrackWidth=0.35
 264 ViaDiameter=1
 265 ViaDrill=0.6
 266 uViaDiameter=0.3
 267 uViaDrill=0.1
 268 dPairWidth=0.2
 269 dPairGap=0.25
 270 dPairViaGap=0.25