8 #define MBOX_READ_REG (*(volatile uint32_t*)(IO_BASE | 0xb880))
9 #define MBOX_POLL_REG (*(volatile uint32_t*)(IO_BASE | 0xb890))
10 #define MBOX_SENDER_REG (*(volatile uint32_t*)(IO_BASE | 0xb894))
11 #define MBOX_STATUS_REG (*(volatile uint32_t*)(IO_BASE | 0xb898))
12 #define MBOX_CFG_REG (*(volatile uint32_t*)(IO_BASE | 0xb89c))
13 #define MBOX_WRITE_REG (*(volatile uint32_t*)(IO_BASE | 0xb8a0))
15 #define MBOX_STAT_WRBUSY 0x80000000
16 #define MBOX_STAT_RDBUSY 0x40000000
19 uint32_t phys_width, phys_height;
20 uint32_t virt_width, virt_height;
21 uint32_t pitch; /* filled by videocore */
24 void *addr; /* filled by videocore */
25 uint32_t size; /* filled by videocore */
28 void mbox_write(int mbox, uint32_t msg);
29 uint32_t mbox_read(int mbox);
31 static struct vc_fbinfo fbinf __attribute__((aligned(16)));
35 memset(&fbinf, 0, sizeof fbinf);
36 fbinf.phys_width = fbinf.virt_width = 1024;
37 fbinf.phys_height = fbinf.virt_height = 600;
39 fbinf.x = fbinf.y = 0;
41 mbox_write(1, MEM_BUS_COHERENT(&fbinf));
42 if(mbox_read(1) != 0) {
43 ser_printstr("Failed to initialize display\n");
47 ser_printstr("Video init successful\n");
48 memset(fbinf.addr, 0, fbinf.size);
52 void mbox_write(int mbox, uint32_t msg)
54 while(MBOX_STATUS_REG & MBOX_STAT_WRBUSY);
55 MBOX_WRITE_REG = (msg & 0xfffffff0) | mbox;
58 uint32_t mbox_read(int mbox)
63 while(MBOX_STATUS_REG & MBOX_STAT_RDBUSY);
65 } while((msg & 0xf) != mbox);
67 return msg & 0xfffffff0;