Raspberry Pi2 notes
===================

Memory access ordering
----------------------
Accessing different peripherals migh return results out of order. See bcm2835
spec section 1.3. Use memory barriers as follows:
 - place write barrier before the first write to a peripheral
 - place read barrier after the last read of a peripheral

Multiple accesses to the same peripheral in a row do not require barriers.

Interrupt handlers should have a read barrier before their first read, and end
with a write barrier.

Cache coherency
---------------
Two types of cache management:
 - cache cleaning (write-back caches)
 - cache invalidation (all caches)

Cache clean and invalidate operations are also needed before the GPU can see our
command buffers... see:
https://github.com/rsta2/uspi/blob/38eaff4f715643a9/lib/synchronize.c

Memory map
----------
RAM is mapped to 0, 40000000 (cache-coherent) and c0000000h (uncached) in VC
space. In the ARM address space is mapped to 0(?).

I/O base is at 7e000000 in VC address space (rpi1?), and mapped to different
ranges for each model in ARM space.

Memory map summary:
 - load address: 8000h
 - I/O base:
   * rpi0/1: 20000000h
   * rpi2/3: 3f000000h
   * rpi4:   fe000000h