; PPU write-only
	REG_INIDISP	= $2100
	REG_OBSEL  	= $2101
	REG_OAMADDL	= $2102
	REG_OAMADDH	= $2103
	REG_OAMDATA	= $2104
	REG_BGMODE 	= $2105
	REG_MOSAIC 	= $2106
	REG_BG1SC  	= $2107
	REG_BG2SC  	= $2108
	REG_BG3SC  	= $2109
	REG_BG4SC  	= $210a
	REG_BG12NBA	= $210b
	REG_BG34NBA	= $210c
	REG_BG1HOFS	= $210d
	REG_BG1VOFS	= $210e
	REG_BG2HOFS	= $210f
	REG_BG2VOFS	= $2110
	REG_BG3HOFS	= $2111
	REG_BG3VOFS	= $2112
	REG_BG4HOFS	= $2113
	REG_BG4VOFS	= $2114
	REG_VMAINC	= $2115
	REG_VMADDL	= $2116
	REG_VMADDH	= $2117
	REG_VMDATAL	= $2118
	REG_VMDATAH	= $2119
	REG_M7SEL	= $211a
	REG_M7A		= $211b
	REG_M7B		= $211c
	REG_M7C		= $211d
	REG_M7D		= $211e
	REG_M7X		= $211f
	REG_M7Y		= $2120
	REG_CGADD	= $2121
	REG_CGDATA	= $2122
	REG_W12SEL	= $2123
	REG_W34SEL	= $2124
	REG_WOBJSEL	= $2125
	REG_WH0		= $2126
	REG_WH1		= $2127
	REG_WH2		= $2128
	REG_WH3		= $2129
	REG_WBGLOG	= $212a
	REG_WOBJLOG	= $212b
	REG_TM		= $212c
	REG_TS		= $212d
	REG_TMW		= $212e
	REG_TSW		= $212f
	REG_CGWSEL	= $2130
	REG_CGADSUB	= $2131
	REG_COLDATA	= $2132
	REG_SETINI	= $2133
	; PPU read-only
	REG_MPYL	= $2134
	REG_MPYM	= $2135
	REG_MPYH	= $2136
	REG_SLHV	= $2137
	REG_RDOAM	= $2138
	REG_RDVRAML	= $2139
	REG_RDVRAMH	= $213a
	REG_RDCGRAM	= $213b
	REG_OPHCT	= $213c
	REG_OPVCT	= $213d
	REG_STAT77	= $213e
	REG_STAT78	= $213f

	REG_NMITIMEN	= $4200
	REG_WRIO	= $4201
	REG_WRMPYA	= $4202
	REG_WRMPYB	= $4203
	REG_WRDIVL	= $4204
	REG_WRDIVH	= $4205
	REG_WRDIVB	= $4206
	REG_HTIMEL	= $4207
	REG_HTIMEH	= $4208
	REG_VTIMEL	= $4209
	REG_VTIMEH	= $420a
	REG_MEMSEL	= $420d

	; DMA
	REG_MDMAEN	= $420b
	REG_HDMAEN	= $420c

	REG_HVBJOY	= $4212

	REG_DMAP_BASE	= $4300
	REG_BBAD_BASE	= $4301
	REG_A1TL_BASE	= $4302
	REG_A1TH_BASE	= $4303
	REG_A1B_BASE	= $4304
	REG_DASL_BASE	= $4305
	REG_DASH_BASE	= $4306
	REG_DASB_BASE	= $4307
	REG_A2AL_BASE	= $4308
	REG_A2AH_BASE	= $4309
	REG_NTRL_BASE	= $430a

	.define REG_DMAP(n)	REG_DMAP_BASE | (n << 4)
	.define REG_BBAD(n)	REG_BBAD_BASE | (n << 4)
	.define REG_A1TL(n)	REG_A1TL_BASE | (n << 4)
	.define REG_A1TH(n)	REG_A1TH_BASE | (n << 4)
	.define REG_A1B(n)	REG_A1B_BASE | (n << 4)
	.define REG_DASL(n)	REG_DASL_BASE | (n << 4)
	.define REG_DASH(n)	REG_DASH_BASE | (n << 4)
	.define REG_DASB(n)	REG_DASB_BASE | (n << 4)
	.define REG_A2AL(n)	REG_A2AL_BASE | (n << 4)
	.define REG_A2AH(n)	REG_A2AH_BASE | (n << 4)
	.define REG_NTRL(n)	REG_NTRL_BASE | (n << 4)


	.macro setreg reg, val
	lda #val
	sta reg
	.endmacro

	.macro fblank onoff
	lda #($0f | (onoff << 7))
	sta REG_INIDISP
	.endmacro

	.macro setpal idx, r, g, b
	setreg REG_CGADD, idx
	setreg REG_CGDATA, (r | g << 5)
	setreg REG_CGDATA, (g >> 3 | b << 2)
	.endmacro

	.macro wait_vblank
@wait_vblank_loop:
	lda REG_HVBJOY
	and #$80
	beq @wait_vblank_loop
	.endmacro

	; vi:ft=asm_ca65: