.p816
	.include "65816.inc"
	.include "hwregs.inc"

	.segment "rodata"
	.include "data.inc"
	.include "sintab.inc"

	.segment "code"

	; VMEM map
	; 0000: tilemap for BG1 (32x32 word tile refs, 2kb)
	; 2048: BG3-base (h/v offsets)
	; 8192: tile data (16k)
	vmem_tiles_offs = 4096	; 4k words
	vmem_hoffs_offs = 1024	; 2k words
	vmem_voffs_offs = vmem_hoffs_offs + 32

	sei
	; get out of 6502 emulation mode
	clc
	xce

	; initialize stack
	I16
	ldx #$1fff
	txs
	I8

	jsr snes_init
	setreg REG_SETINI, $4	; 239 lines
	setreg REG_BGMODE, $02	; mode 2, 8x8 tiles
	setreg REG_BG12NBA, $1	; tiles at offs 8kb
	setreg REG_TM, $1	; main screen: BG1
	setreg REG_BG3SC, (vmem_hoffs_offs / 1024) << 2

	ldx #0
cmap_loop:
	txa
	lsr
	sta REG_CGADD
	lda logo4bpp_cmap,x
	inx
	sta REG_CGDATA
	lda logo4bpp_cmap,x
	inx
	sta REG_CGDATA
	cpx #32		; 16 entries 2 bytes each
	bne cmap_loop

	pea logo4bpp_tiles_width * logo4bpp_tiles_height / 2
	pea logo4bpp_tiles
	pea vmem_tiles_offs
	jsr copy_vmem
	A16
	pla
	pla
	pla
	A8

	pea logo4bpp_tilemap_rows * logo4bpp_tilemap_cols * 2
	pea logo4bpp_tilemap
	pea 0
	jsr copy_vmem
	A16
	pla
	pla
	pla
	A8

	fblank 0

	; main loop
	nframe = 0
	ncol = 2
	anim = 4
	vscroll = 8
	shadow_voffs = 32

	A16
	stz nframe
mainloop:
	lda nframe
	lsr
	lsr
	sta anim
	inc nframe
	A8

	stz ncol
@cloop:
	lda anim
	clc
	adc ncol
	asl
	tax
	lda sintab,x
	sec
	sbc #128
	asr
	asr
	asr

	ldx ncol
	bne @per_tile_offs
	; global scroll for the first column
	sta vscroll
	bra @end

@per_tile_offs:
	pha
	lda ncol
	asl
	tax	; x = ncol << 1
	pla
	sta shadow_voffs,x
	inx
	lda #$20
	sta shadow_voffs,x
@end:
	inc ncol
	lda ncol
	and #$1f
	bne @cloop

	; wait for vblank, and DMA the table to vmem
	wait_vblank
	fblank 1
	lda vscroll
	sta REG_BG1VOFS
	stz REG_BG1VOFS
	lda #(vmem_voffs_offs & $ff)
	sta REG_VMADDL
	lda #(vmem_voffs_offs >> 8)
	sta REG_VMADDH
	setreg REG_MDMAEN, 0
	setreg REG_DMAP(0), $01			; A->B words at X,X+1, A inc
	setreg REG_BBAD(0), REG_VMDATAL & $ff	; write to VMDATAL,VMDATAH
	setreg REG_A1TL(0), shadow_voffs
	setreg REG_A1TH(0), 0
	setreg REG_A1B(0), 0
	setreg REG_DASL(0), 64
	setreg REG_DASH(0), 0
	setreg REG_DASB(0), 0
	setreg REG_MDMAEN, 1			; enable DMA channel 0
	fblank 0
	A16
	jmp mainloop

	; copy_vmem(vmem_offset, src, num_bytes)
copy_vmem:
	rep #$30	; 16bit accumulator and index registers
	.a16
	.i16
	phd		; save d
	tsc		; and make it point to the stack
	tcd
	A8	; restore 8bit accum
	; stack frame
	; $1 saved D
	; $3 return address
	; $5 vmem_offs
	; $7 src
	; $9 num_bytes

	lda #$80	; auto incerment after wiriting high byte
	sta REG_VMAINC
	lda $5
	sta REG_VMADDL
	lda $6
	sta REG_VMADDH
	ldy #0
@loop:
	lda ($7),y
	sta REG_VMDATAL
	iny
	lda ($7),y
	sta REG_VMDATAH
	iny
	cpy $9
	bne @loop
	
	pld
	I8		; back to 8bit index registers
	rts


snes_init:
	fblank 1
	stz REG_OBSEL
	stz REG_OAMADDL
	stz REG_OAMADDH
	stz REG_OAMDATA
	stz REG_OAMDATA
	stz REG_BGMODE
	stz REG_MOSAIC
	stz REG_BG1SC
	stz REG_BG2SC
	stz REG_BG3SC
	stz REG_BG4SC
	stz REG_BG12NBA
	stz REG_BG34NBA
	stz REG_BG1HOFS
	stz REG_BG1HOFS
	stz REG_BG1VOFS
	stz REG_BG1VOFS
	stz REG_BG2HOFS
	stz REG_BG2HOFS
	stz REG_BG2VOFS
	stz REG_BG2VOFS
	stz REG_BG3HOFS
	stz REG_BG3HOFS
	stz REG_BG3VOFS
	stz REG_BG3VOFS
	stz REG_BG4HOFS
	stz REG_BG4HOFS
	stz REG_BG4VOFS
	stz REG_BG4VOFS
	setreg REG_VMAINC, $80
	stz REG_VMADDL
	stz REG_VMADDH
	stz REG_VMDATAL
	stz REG_VMDATAH
	stz REG_M7SEL
	stz REG_M7A
	stz REG_M7A
	stz REG_M7B
	stz REG_M7B
	stz REG_M7C
	stz REG_M7C
	stz REG_M7D
	stz REG_M7D
	stz REG_M7X
	stz REG_M7X
	stz REG_M7Y
	stz REG_M7Y
	stz REG_CGADD
	stz REG_CGDATA
	stz REG_CGDATA
	stz REG_W12SEL
	stz REG_W34SEL
	stz REG_WH0
	stz REG_WH1
	stz REG_WH2
	stz REG_WH3
	stz REG_WBGLOG
	stz REG_WOBJLOG
	stz REG_TM
	stz REG_TS
	stz REG_TMW
	stz REG_TSW
	setreg REG_CGWSEL, $30
	stz REG_CGADSUB
	setreg REG_COLDATA, $e0
	stz REG_SETINI
	stz REG_NMITIMEN
	setreg REG_WRIO, $ff
	stz REG_WRMPYA
	stz REG_WRMPYB
	stz REG_WRDIVL
	stz REG_WRDIVH
	stz REG_WRDIVB
	stz REG_HTIMEL
	stz REG_HTIMEH
	stz REG_VTIMEL
	stz REG_VTIMEH
	stz REG_MDMAEN
	stz REG_HDMAEN
	stz REG_MEMSEL

	; clear vmem
	I16
	setreg REG_VMAINC, $80
	ldx $4000
@clear:	stz REG_VMDATAL
	stz REG_VMDATAH
	dex
	bne @clear
	I8
	rts

	; cartridge header
	.segment "carthdr"
	.byte "TEST                 "
	.byte $20	; fast ROM, LoROM mapping
	.byte 0		; ROM only
	.byte 1		; ROM banks 1 = 32k
	.byte 0		; RAM size
	.byte 2		; country europe/oceania/asia
	.byte 0		; developer id: none
	.byte 0		; ROM version
	.word $ffff	; checksum complement
	.word 0		; checksum
	; 65816 vectors
	.word 0, 0
	.word 0		; cop
	.word 0		; brk
	.word 0		; abort
	.word 0		; NMI (vblank)
	.word 0
	.word 0		; IRQ
	; 6502 vectors
	.word 0, 0
	.word 0		; cop
	.word 0
	.word 0		; abort
	.word 0		; NMI (vblank)
	.word $8000	; reset
	.word 0		; IRQ/BRK


	; vi:ft=asm_ca65: