From: John Tsiombikas Date: Fri, 1 May 2020 03:18:46 +0000 (+0300) Subject: - reorganized project directory structure X-Git-Url: http://git.mutantstargoat.com/user/nuclear/?p=z80comp2;a=commitdiff_plain - reorganized project directory structure - merged ROM monitor code - merged emulator - expanded README and added license files --- diff --git a/.gitignore b/.gitignore index b9f3525..eeb0f87 100644 --- a/.gitignore +++ b/.gitignore @@ -1,3 +1,5 @@ +*.o +*.d *.swp *.chp *.fus @@ -6,3 +8,6 @@ *.pdf *.sch-bak *.dcm +rom/monitor +*.lst +emu/z80v2emu diff --git a/LICENSE.hw b/LICENSE.hw new file mode 100644 index 0000000..fd662a7 --- /dev/null +++ b/LICENSE.hw @@ -0,0 +1,428 @@ +Attribution-ShareAlike 4.0 International + +======================================================================= + +Creative Commons Corporation ("Creative Commons") is not a law firm and +does not provide legal services or legal advice. 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If not, see . + +Also add information on how to contact you by electronic and paper mail. + + If the program does terminal interaction, make it output a short +notice like this when it starts in an interactive mode: + + Copyright (C) + This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, your program's commands +might be different; for a GUI interface, you would use an "about box". + + You should also get your employer (if you work as a programmer) or school, +if any, to sign a "copyright disclaimer" for the program, if necessary. +For more information on this, and how to apply and follow the GNU GPL, see +. + + The GNU General Public License does not permit incorporating your program +into proprietary programs. If your program is a subroutine library, you +may consider it more useful to permit linking proprietary applications with +the library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License. But first, please read +. diff --git a/Makefile b/Makefile deleted file mode 100644 index 3b18b75..0000000 --- a/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -glue.jed: glue.pld - -%.jed: %.pld - galasm $< - -.PHONY: program -program: glue.jed - minipro -p ATF16V8B -c config -w $< diff --git a/README.md b/README.md index ea74067..c2c153f 100644 --- a/README.md +++ b/README.md @@ -1,8 +1,32 @@ -Z80 micro 2 -=========== -This is a simple Z80 computer: +Z80 computer v2 +=============== + +About +----- +This is a simple Z80 computer. Hopefully I'll find a better name for it. - 3.6864 MHz clock (see mc68681 DUART) - 64kb RAM (32kb accessible at any single time) - 32kb ROM - Dual serial UART (mc68681) with CTS/RTS flow control (1x RS232, 1x TTL-level) - Glue logic implemented in a ATF16V8 GAL (glue.pld) + +Directory structure: + - `hw/`: hardware design files, schematic, and GAL equations + - `rom/`: source code of the ROM monitor program + - `emu/`: system emulator + +License +------- +Copyright (C) 2020 John Tsiombikas + +Hardware designs are open hardware, released under the terms of the Creative +Commons Attribution Share-Alike license (CC BY-SA). See `LICENSE.hw` for +details. + +All software and firmware in this project is free software, released under the +terms of the GNU General Public License v3, or at your option any later version +published by the Free Software Foundation. See `LICENSE.sw` for details. + +In short you are free to use, reproduce, modify, and/or redistribute any part of +this project, provided you also extend the same freedom, under the same terms, +to anyone receiving this, or any derivative work based on this, from you. diff --git a/emu/Makefile b/emu/Makefile new file mode 100644 index 0000000..d0a5af4 --- /dev/null +++ b/emu/Makefile @@ -0,0 +1,15 @@ +src = $(wildcard src/*.c) +obj = $(src:.c=.o) +dep = $(obj:.o=.d) +bin = z80v2emu + +CFLAGS = -pedantic -Wall -g -MMD + +$(bin): $(obj) + $(CC) -o $@ $(obj) $(LDFLAGS) + +-include $(dep) + +.PHONY: clean +clean: + rm -f $(obj) $(bin) diff --git a/emu/src/cpu.c b/emu/src/cpu.c new file mode 100644 index 0000000..ce24dcc --- /dev/null +++ b/emu/src/cpu.c @@ -0,0 +1,784 @@ +#include +#include "cpu.h" +#include "emu.h" + +enum { + FLAGS_C = 0x01, + FLAGS_N = 0x02, + FLAGS_PV = 0x04, + FLAGS_H = 0x10, + FLAGS_Z = 0x40, + FLAGS_S = 0x80 +}; + +enum { + R_B = 0, + R_C = 1, + R_D = 2, + R_E = 3, + R_H = 4, + R_L = 5, + R_INVAL = 6, + R_A = 7 +}; + +#define RRSET2 4 +enum { + RR_BC = 0, + RR_DE = 1, + RR_HL = 2, + RR_SP = 3, + + RR2_BC = RRSET2 | RR_BC, + RR2_DE = RRSET2 | RR_DE, + RR2_HL = RRSET2 | RR_HL, + RR2_AF = RRSET2 | RR_SP +}; + +enum { + PREFIX_ED = 1, + PREFIX_CB = 2, + PREFIX_DD = 4, + PREFIX_FD = 8 +}; + +enum { + ALUOP_ADD = 0, + ALUOP_ADC = 1, + ALUOP_SUB = 2, + ALUOP_SBC = 3, + ALUOP_AND = 4, + ALUOP_XOR = 5, + ALUOP_OR = 6, + ALUOP_CP = 7 +}; + +enum { + CC_NZ = 0, + CC_Z = 1, + CC_NC = 2, + CC_C = 3, + CC_PO = 4, + CC_PE = 5, + CC_P = 6, + CC_M = 7 +}; + +struct regs8 { + uint8_t a, f, b, c, d, e, h, l; +}; +struct regs16 { + uint16_t af, bc, de, hl; +}; + +union genregs { + struct regs8 r; + struct regs16 rr; +}; + +struct registers { + union genregs g, shadow; /* general purpose and shadow registers */ + uint8_t i, r; + uint16_t ix, iy, sp, pc; + uint8_t iff, imode; +}; + +static void runop_main(uint8_t op); +static void runop_ed(uint8_t op); +static void runop_cb(uint8_t op); +static void runop_dd(uint8_t op); +static void runop_fd(uint8_t op); +static void runop_ddcb(uint8_t op); +static void runop_fdcb(uint8_t op); + +static void op_load_reg8_reg8(int rdest, int rsrc); +static void op_load_reg8_imm8(int rdest, uint8_t imm); +static void op_load_reg8_mem(int rdest, uint16_t addr); +static void op_store_mem_reg8(uint16_t addr, int rsrc); +static void op_store_mem_imm8(uint16_t addr, uint8_t imm); +static void op_store_mem_reg16(uint16_t addr, int rsrc); +static void op_load_reg16_imm16(int rdest, uint16_t imm); +static void op_load_reg16_reg16(int rdest, int rsrc); +static void op_exch_mem_reg16(uint16_t addr, int rr); +static void op_alu_reg8(int op, int r); +static void op_alu_imm8(int op, uint8_t imm); +static void op_incdec_reg8(int r, int adj); +static void op_incdec_reg16(int r, int adj); +static void op_incdec_mem(uint16_t addr, int adj); +static void op_add_reg16_reg16(int rdest, int rsrc); +static void op_rl_reg8(int r, int width); +static void op_rr_reg8(int r, int width); +static void op_push_reg16(int r); +static void op_pop_reg16(int r); +static void op_call(uint16_t addr); +static void op_ret(void); +static void op_input(int r, uint16_t addr); +static void op_output(uint16_t addr, int r); + +static struct registers regs; +static int halt; + +static void (*runop[16])(uint8_t op) = { + runop_main, /* 0000: no prefix */ + runop_ed, /* 0001: ED prefix */ + runop_cb, /* 0010: CB prefix */ + 0, /* 0011: CBED invalid */ + runop_dd, /* 0100: DD prefix */ + 0, /* 0101: DDED invalid */ + runop_ddcb, /* 0110: DDCB prefix */ + 0, /* 0111: DDCBED invalid */ + runop_fd, /* 1000: FD prefix */ + 0, /* 1001: FDED invalid */ + runop_fdcb, /* 1010: FDCB prefix */ + 0, 0, 0, 0, 0 /* all the rest combinations are invalid */ +}; + +static uint8_t *regptr8[8] = { + ®s.g.r.b, ®s.g.r.c, + ®s.g.r.d, ®s.g.r.e, + ®s.g.r.h, ®s.g.r.l, + 0, ®s.g.r.a +}; + +static uint16_t *regptr16[] = { + ®s.g.rr.bc, + ®s.g.rr.de, + ®s.g.rr.hl, + ®s.sp, + + ®s.g.rr.bc, + ®s.g.rr.de, + ®s.g.rr.hl, + ®s.g.rr.af +}; + +void cpu_reset(void) +{ + regs.iff = 0; + regs.pc = 0; + regs.i = regs.r = 0; + regs.imode = 0; +} + +static uint8_t fetch_byte(void) +{ + return emu_mem_read(regs.pc++); +} + +static uint16_t fetch_imm16(void) +{ + uint16_t lsb = emu_mem_read(regs.pc++); + uint16_t msb = emu_mem_read(regs.pc++); + return lsb | (msb << 8); +} + +static unsigned int prefix_bit(uint8_t op) +{ + switch(op) { + case 0xed: return PREFIX_ED; + case 0xcb: return PREFIX_CB; + case 0xdd: return PREFIX_DD; + case 0xfd: return PREFIX_FD; + default: + break; + } + return 0; +} + +void cpu_step(void) +{ + unsigned int pbit, prefix = 0; + uint8_t op; + + if(halt) return; + + op = fetch_byte(); + if((pbit = prefix_bit(op))) { + prefix = pbit; + op = fetch_byte(); + + /* only treat the next byte as another prefix if the previous was dd or fd */ + if((pbit = prefix_bit(op)) && (prefix == 0xdd || prefix == 0xfd)) { + prefix |= pbit; + op = fetch_byte(); + } + } + + if(runop[prefix]) { + runop[prefix](op); + } +} + +static int cond(int cc) +{ + switch(cc) { + case CC_NZ: return ~regs.g.r.f & FLAGS_Z; + case CC_Z: return regs.g.r.f & FLAGS_Z; + case CC_NC: return ~regs.g.r.f & FLAGS_C; + case CC_C: return regs.g.r.f & FLAGS_C; + case CC_PO: return ~regs.g.r.f & FLAGS_PV; + case CC_PE: return regs.g.r.f & FLAGS_PV; + case CC_P: return ~regs.g.r.f & FLAGS_S; + case CC_M: return regs.g.r.f & FLAGS_S; + default: + break; + } + return 0; +} + +#define ALUOP(x) (((x) >> 3) & 7) +#define DEST_R(x) (((x) >> 3) & 7) +#define OPCOND(x) (((x) >> 3) & 7) +#define SRC_R(x) ((x) & 7) +#define OP_RR(x) (((x) >> 4) & 3) +#define RST_ADDR(x) ((x) & 0x38) + +#define SWAP_RR(a, b) \ + do { \ + uint16_t tmp = a; \ + a = b; \ + b = tmp; \ + } while(0) + +static void runop_main(uint8_t op) +{ + int b67 = op >> 6; + uint8_t disp; + uint16_t addr; + + switch(op) { + /* 8-bit load group except ld r,r/ld r,imm/ld r,(hl)/ld (hl),r in default */ + case 0x36: + op_store_mem_imm8(regs.g.rr.hl, fetch_byte()); + break; + case 0x0a: + op_load_reg8_mem(R_A, regs.g.rr.bc); + break; + case 0x1a: + op_load_reg8_mem(R_A, regs.g.rr.de); + break; + case 0x3a: + op_load_reg8_mem(R_A, fetch_imm16()); + break; + case 0x02: + op_store_mem_reg8(regs.g.rr.bc, R_A); + break; + case 0x12: + op_store_mem_reg8(regs.g.rr.de, R_A); + break; + case 0x32: + op_store_mem_reg8(fetch_imm16(), R_A); + break; + + /* 16-bit load group */ + case 0x01: + case 0x11: + case 0x21: + case 0x31: + op_load_reg16_imm16(OP_RR(op), fetch_imm16()); + break; + case 0x2a: + op_load_reg16_imm16(RR_HL, fetch_imm16()); + break; + case 0x22: + op_store_mem_reg16(fetch_imm16(), RR_HL); + break; + case 0xf9: + op_load_reg16_reg16(RR_SP, RR_HL); + break; + case 0xc5: + case 0xd5: + case 0xe0: + case 0xf5: + op_push_reg16(RRSET2 | OP_RR(op)); + break; + case 0xc1: + case 0xd1: + case 0xe1: + case 0xf1: + op_pop_reg16(RRSET2 | OP_RR(op)); + break; + + /* exchange, block transfer, block search groups */ + case 0xeb: + SWAP_RR(regs.g.rr.de, regs.g.rr.hl); + break; + case 0x08: + SWAP_RR(regs.g.rr.af, regs.shadow.rr.af); + break; + case 0xd9: + SWAP_RR(regs.g.rr.bc, regs.shadow.rr.bc); + SWAP_RR(regs.g.rr.de, regs.shadow.rr.de); + SWAP_RR(regs.g.rr.hl, regs.shadow.rr.hl); + break; + case 0xe3: + op_exch_mem_reg16(regs.sp, RR_HL); + break; + + /* general purpose arithmetic and cpu control groups */ + case 0x27: + break; /* TODO implement DAA */ + case 0x2f: /* cpl a */ + regs.g.r.a = ~regs.g.r.a; + regs.g.r.f |= FLAGS_H | FLAGS_N; + break; + case 0x3f: /* ccf */ + regs.g.r.f ^= FLAGS_C; + break; + case 0x37: /* scf */ + regs.g.r.f |= FLAGS_C; + case 0x00: /* nop */ + break; + case 0x76: /* halt */ + halt = 1; + break; + case 0xf3: /* di */ + regs.iff = 0; + break; + case 0xfb: /* ei */ + regs.iff = 1; + break; + + /* 16-bit arithmetic group */ + case 0x09: + case 0x19: + case 0x29: + case 0x39: + op_add_reg16_reg16(RR_HL, OP_RR(op)); + break; + case 0x03: + case 0x13: + case 0x23: + case 0x33: + op_incdec_reg16(OP_RR(op), 1); + break; + case 0x0b: + case 0x1b: + case 0x2b: + case 0x3b: + op_incdec_reg16(OP_RR(op), -1); + break; + + /* rotate and shift group */ + case 0x07: /* rlca */ + op_rl_reg8(R_A, 8); + break; + case 0x17: /* rla */ + op_rl_reg8(R_A, 9); + break; + case 0x0f: /* rrca */ + op_rr_reg8(R_A, 8); + break; + case 0x1f: /* rra */ + op_rr_reg8(R_A, 9); + break; + + /* jump group except jp cc, imm16 in default */ + case 0xc3: /* jp imm16 */ + regs.pc = fetch_imm16(); + break; + case 0x18: /* jr imm8 */ + regs.pc += fetch_byte(); + break; + case 0x38: /* jr c, imm8 */ + disp = fetch_byte(); + if(cond(CC_C)) regs.pc += disp; + break; + case 0x30: /* jr nc, imm8 */ + disp = fetch_byte(); + if(cond(CC_NC)) regs.pc += disp; + break; + case 0x28: /* jr z, imm8 */ + disp = fetch_byte(); + if(cond(CC_Z)) regs.pc += disp; + break; + case 0x20: /* jr nz, imm8 */ + disp = fetch_byte(); + if(cond(CC_NZ)) regs.pc += disp; + break; + case 0xe9: /* jp (hl) */ + regs.pc = regs.g.rr.hl; + break; + case 0x10: /* djnz, imm8 */ + disp = fetch_byte(); + if(--regs.g.r.b) regs.pc += disp; + break; + + /* call and return group except call cc,imm16/ret cc,imm16/rst */ + case 0xcd: + op_call(fetch_imm16()); + break; + case 0xc9: + op_ret(); + break; + + /* input and output group */ + case 0xdb: + op_input(R_A, ((uint16_t)regs.g.r.a << 8) | fetch_byte()); + break; + case 0xd3: + op_output(((uint16_t)regs.g.r.a << 8) | fetch_byte(), R_A); + break; + + default: + switch(b67) { + case 0: + if(SRC_R(op) == 6) { + op_load_reg8_imm8(DEST_R(op), fetch_byte()); + } else if(SRC_R(op) == 4 || SRC_R(op) == 5) { + int adj = (op & 1) ? -1 : 1; + if(DEST_R(op) != 6) { + op_incdec_reg8(DEST_R(op), adj); + } else { + op_incdec_mem(regs.g.rr.hl, adj); + } + } + break; + + case 1: + if(DEST_R(op) != 6 && SRC_R(op) != 6) { + op_load_reg8_reg8(DEST_R(op), SRC_R(op)); + } else { + if(SRC_R(op) == 6) { + op_load_reg8_mem(DEST_R(op), regs.g.rr.hl); + } else if(DEST_R(op) == 6) { + op_store_mem_reg8(regs.g.rr.hl, SRC_R(op)); + } + } + break; + + case 2: + if(SRC_R(op) != 6) { + op_alu_reg8(ALUOP(op), SRC_R(op)); + } + break; + + case 3: + if(SRC_R(op) == 6) { /* alu-op a, imm8 */ + op_alu_imm8(ALUOP(op), fetch_byte()); + + } else if(SRC_R(op) == 2) { /* jp cc, imm16 */ + addr = fetch_imm16(); + if(cond(OPCOND(op))) { + regs.pc = addr; + } + + } else if(SRC_R(op) == 4) { /* call cc, imm16 */ + addr = fetch_imm16(); + if(cond(OPCOND(op))) op_call(addr); + + } else if(SRC_R(op) == 0) { /* ret cc, imm16 */ + addr = fetch_imm16(); + if(cond(OPCOND(op))) op_ret(); + + } else if(SRC_R(op) == 7) { /* rst */ + op_call(RST_ADDR(op)); + } + break; + + default: + break; + } + + break; /* treat any unknown opcodes as nops */ + } +} + +static void runop_ed(uint8_t op) +{ +} + +static void runop_cb(uint8_t op) +{ +} + +static void runop_dd(uint8_t op) +{ +} + +static void runop_fd(uint8_t op) +{ +} + +static void runop_ddcb(uint8_t op) +{ +} + +static void runop_fdcb(uint8_t op) +{ +} + +static void set_reg8(int r, uint8_t val) +{ + *regptr8[r] = val; +} + +static void set_reg8s(int r, int8_t val) +{ + *regptr8[r] = *(uint8_t*)&val; +} + +static uint8_t get_reg8(int r) +{ + return *regptr8[r]; +} + +static int8_t get_reg8s(int r) +{ + return *(int8_t*)regptr8[r]; +} + +static void set_reg16(int r, uint16_t val) +{ + *regptr16[r] = val; +} + +static void set_reg16s(int r, int16_t val) +{ + *regptr16[r] = *(uint16_t*)&val; +} + +static uint16_t get_reg16(int r) +{ + return *regptr16[r]; +} + +static int16_t get_reg16s(int r) +{ + return *(int16_t*)regptr16[r]; +} + +static void set_flag(unsigned int flag, int val) +{ + if(val) { + regs.g.r.f |= flag; + } else { + regs.g.r.f &= ~flag; + } +} + +static int parity(int x) +{ + int i, s = 0; + for(i=0; i<8; i++) { + s += x & 1; + x >>= 1; + } + return s & 1; +} + +static int overflow(int x) +{ + return x > 127 || x < -128; +} + +static int overflow16(int x) +{ + return x > 32767 || x < -32768; +} + +static void op_load_reg8_reg8(int rdest, int rsrc) +{ + set_reg8(rdest, get_reg8(rsrc)); +} + +static void op_load_reg8_imm8(int rdest, uint8_t imm) +{ + set_reg8(rdest, imm); +} + +static void op_load_reg8_mem(int rdest, uint16_t addr) +{ + set_reg8(rdest, emu_mem_read(addr)); +} + +static void op_store_mem_reg8(uint16_t addr, int rsrc) +{ + emu_mem_write(addr, get_reg8(rsrc)); +} + +static void op_store_mem_imm8(uint16_t addr, uint8_t imm) +{ + emu_mem_write(addr, imm); +} + +static void op_store_mem_reg16(uint16_t addr, int rsrc) +{ + uint16_t val = get_reg16(rsrc); + emu_mem_write(addr, val); + emu_mem_write(addr + 1, val >> 8); +} + +static void op_load_reg16_imm16(int rdest, uint16_t imm) +{ + set_reg16(rdest, imm); +} + +static void op_load_reg16_reg16(int rdest, int rsrc) +{ + set_reg16(rdest, get_reg16(rsrc)); +} + +static void op_exch_mem_reg16(uint16_t addr, int rr) +{ + uint16_t val = get_reg16(rr); + uint16_t lsb = emu_mem_read(addr); + uint16_t msb = emu_mem_read(addr + 1); + set_reg16(rr, lsb | (msb << 8)); + emu_mem_write(addr, val); + emu_mem_write(addr + 1, val >> 8); +} + +#define CARRY (regs.g.r.f & 1) + +static void op_alu_reg8(int op, int r) +{ + op_alu_imm8(op, get_reg8(r)); +} + +static void op_alu_imm8(int op, uint8_t imm) +{ + int c, h, pv, n = 0; + int acc = get_reg8s(R_A); + int rval = *(int8_t*)&imm; + c = CARRY; + + switch(op) { + case ALUOP_ADD: + if(0) { + case ALUOP_SUB: + case ALUOP_CP: + rval = -rval; + c = -c; + n = 1; + } + h = ((acc & 0xf) + (rval + 0xf)) & 0x10; + acc += rval; + c = acc & 0x100; + pv = overflow(acc); + break; + + case ALUOP_ADC: + if(0) { + case ALUOP_SBC: + rval = -rval; + c = -c; + n = 1; + } + h = ((acc & 0xf) + (rval + 0xf) + CARRY) & 0x10; + acc += rval + CARRY; + c = acc & 0x100; + pv = overflow(acc); + break; + + case ALUOP_AND: + acc &= rval; + c = 0; + h = 1; + pv = parity(acc); + break; + case ALUOP_XOR: + acc ^= rval; + c = 0; + h = 0; + pv = parity(acc); + break; + case ALUOP_OR: + acc |= rval; + c = 0; + h = 0; + pv = parity(acc); + break; + default: + return; + } + + set_flag(FLAGS_S, acc & 0x80); + set_flag(FLAGS_Z, acc == 0); + set_flag(FLAGS_H, h); + set_flag(FLAGS_PV, pv); + set_flag(FLAGS_N, n); + set_flag(FLAGS_C, c); + + if(op != ALUOP_CP) { + set_reg8s(R_A, acc); + } +} + +static void op_incdec_reg8(int r, int adj) +{ + int prev = get_reg8s(r); + int val = prev + adj; + + set_flag(FLAGS_S, val & 0x80); + set_flag(FLAGS_Z, val == 0); + set_flag(FLAGS_H, ((prev & 0xf) + adj) & 0x10); + set_flag(FLAGS_PV, overflow(val)); + set_flag(FLAGS_N, adj < 0); + + set_reg8s(r, val); +} + +static void op_incdec_reg16(int r, int adj) +{ + set_reg16s(r, get_reg16s(r) + adj); +} + +static void op_incdec_mem(uint16_t addr, int adj) +{ + uint16_t lsb = emu_mem_read(addr); + uint16_t msb = emu_mem_read(addr + 1); + int prev, val; + + lsb |= msb << 8; + prev = *(int16_t*)&lsb; + val = prev + adj; + + set_flag(FLAGS_S, val & 0x8000); + set_flag(FLAGS_Z, val == 0); + set_flag(FLAGS_H, ((prev & 0xfff) + adj) & 0x1000); + set_flag(FLAGS_PV, overflow16(val)); + set_flag(FLAGS_N, adj < 0); + + lsb = *(uint16_t*)&val; + emu_mem_write(addr, lsb); + emu_mem_write(addr + 1, lsb >> 8); +} + +static void op_add_reg16_reg16(int rdest, int rsrc) +{ +} + +static void op_rl_reg8(int r, int width) +{ +} + +static void op_rr_reg8(int r, int width) +{ +} + +static void op_push_reg16(int r) +{ +} + +static void op_pop_reg16(int r) +{ +} + +static void op_call(uint16_t addr) +{ +} + +static void op_ret(void) +{ +} + +static void op_input(int r, uint16_t addr) +{ + set_reg8(r, emu_io_read(addr)); +} + +static void op_output(uint16_t addr, int r) +{ + emu_io_write(addr, get_reg8(r)); +} diff --git a/emu/src/cpu.h b/emu/src/cpu.h new file mode 100644 index 0000000..f9f5b4d --- /dev/null +++ b/emu/src/cpu.h @@ -0,0 +1,7 @@ +#ifndef CPU_H_ +#define CPU_H_ + +void cpu_reset(void); +void cpu_step(void); + +#endif /* CPU_H_ */ diff --git a/emu/src/duart.c b/emu/src/duart.c new file mode 100644 index 0000000..35e2312 --- /dev/null +++ b/emu/src/duart.c @@ -0,0 +1,169 @@ +#include "duart.h" +#include "emu.h" + +enum { + REG_MRA = 0x0, + REG_SRA_CSRA = 0x1, + REG_CRA = 0x2, + REG_RBA_TBA = 0x3, + REG_IPCR_ACR = 0x4, + REG_ISR_IMR = 0x5, + REG_CUR_CTUR = 0x6, + REG_CLR_CTLR = 0x7, + REG_MRB = 0x8, + REG_SRB_CSRB = 0x9, + REG_CRB = 0xa, + REG_RBB_TBB = 0xb, + REG_IVR = 0xc, + REG_IP_OPCR = 0xd, + REG_CSTART_OPSET= 0xe, + REG_CSTOP_OPCLR = 0xf +}; + +enum { + CMD_RX_ONOFF = 0x03, + CMD_TX_ONOFF = 0x0c, + CMD_RST_MPTR = 0x10, + CMD_RST_RX = 0x20, + CMD_RST_TX = 0x30, + CMD_RST_ERR = 0x40, + CMD_RST_BRKINT = 0x50, + CMD_START_BRK = 0x60, + CMD_STOP_BRK = 0x70 +}; + +enum { + STAT_RXRDY = 0x01, + STAT_FFULL = 0x02, + STAT_TXRDY = 0x04, + STAT_TXEMPTY = 0x08, + STAT_ERR_OVR = 0x10, + STAT_ERR_PAR = 0x20, + STAT_ERR_FRM = 0x40, + STAT_ERR_BRK = 0x80 +}; + +struct port { + uint8_t mode[2]; + uint8_t clksel; + int modeptr; + int tx, rx; + uint8_t rxfifo[4]; + int rxfifo_in, rxfifo_out; + +}; + +static struct port port[2]; +static uint8_t reg_ipcr; +static uint8_t reg_auxctl; +static uint8_t reg_istat; +static uint8_t reg_imask; +static uint16_t reg_count; +static uint8_t reg_ivec; +static uint8_t reg_opcr; +static uint8_t oport; + +void duart_reset(void) +{ + int i; + + reg_imask = 0; + reg_istat = 0; + reg_opcr = 0; + reg_ivec = 0xf; + oport = 0; + + for(i=0; i<2; i++) { + port[i].mode[0] = port[i].mode[1] = 0; + port[i].modeptr = 0; + port[i].tx = port[i].rx = 0; + port[i].rxfifo_in = port[i].rxfifo_out = 0; + } +} + +void duart_serin(int port, int c) +{ +} + +static int tx_ready(int pidx) +{ + return port[pidx].tx; +} + +static int rx_ready(int pidx) +{ + return port[pidx].rxfifo_in != port[pidx].rxfifo_out; +} + +static int rx_full(int pidx) +{ + return ((port[pidx].rxfifo_in + 1) & 3) == port[pidx].rxfifo_out; +} + +static void command(int pidx, uint8_t data) +{ + if(data & CMD_RX_ONOFF) { + port[pidx].rx = (data & CMD_RX_ONOFF) == 1; + } + if(data & CMD_TX_ONOFF) { + port[pidx].tx = (data & CMD_TX_ONOFF) == 4; + } + switch(data & 0xf0) { + case CMD_RST_MPTR: + port[pidx].modeptr = 0; + break; + + default: + break; + } +} + +uint8_t duart_read(int rs) +{ + uint8_t res; + int pidx = (rs >> 3) & 1; + + switch(rs) { + case REG_SRA_CSRA: + case REG_SRB_CSRB: + res = STAT_TXEMPTY | STAT_TXRDY; + if(rx_ready(pidx)) { + res |= STAT_RXRDY; + } + if(rx_full(pidx)) { + res |= STAT_FFULL; + } + return res; + + default: + break; + } + return 0; +} + +void duart_write(int rs, uint8_t data) +{ + int mptr; + int pidx = (rs >> 3) & 1; + + switch(rs) { + case REG_CRA: + case REG_CRB: + command(pidx, data); + break; + + case REG_MRA: + case REG_MRB: + mptr = port[pidx].modeptr; + port[pidx].mode[mptr] = data; + if(!mptr) port[pidx].modeptr = 1; + break; + + case REG_RBA_TBA: + case REG_RBB_TBB: + if(tx_ready(pidx)) { + emu_serout(pidx, data); + } + break; + } +} diff --git a/emu/src/duart.h b/emu/src/duart.h new file mode 100644 index 0000000..f2e125b --- /dev/null +++ b/emu/src/duart.h @@ -0,0 +1,12 @@ +#ifndef DUART_H_ +#define DUART_H_ + +#include + +void duart_reset(void); +void duart_serin(int port, int c); + +uint8_t duart_read(int rs); +void duart_write(int rs, uint8_t data); + +#endif /* DUART_H_ */ diff --git a/emu/src/emu.c b/emu/src/emu.c new file mode 100644 index 0000000..01f798a --- /dev/null +++ b/emu/src/emu.c @@ -0,0 +1,74 @@ +#include +#include "emu.h" +#include "cpu.h" +#include "duart.h" + +#define RAM_SIZE 0x8000 +static uint8_t ram[RAM_SIZE]; +static uint8_t *rom; +static int rom_size; + +int emu_init(void *romimg, int romsz) +{ + rom = romimg; + rom_size = romsz; + + emu_reset(); + return 0; +} + +void emu_reset(void) +{ + cpu_reset(); + duart_reset(); +} + +void emu_cleanup(void) +{ +} + +void emu_step(void) +{ + cpu_step(); +} + +uint8_t emu_mem_read(uint16_t addr) +{ + if(addr & 0x8000) { /* RAM */ + return ram[addr & 0x7fff]; + } else { /* ROM */ + if((int)addr < rom_size) { + return rom[addr]; + } + } + return 0; +} + +void emu_mem_write(uint16_t addr, uint8_t data) +{ + if(addr & 0x8000) { + ram[addr & 0x7fff] = data; + } +} + +uint8_t emu_io_read(uint16_t addr) +{ + if((addr & 0xf0) == 0) { + return duart_read(addr & 0xf); + } + + /* nothing is enabled, the bus floats, return random bits */ + return rand(); +} + +void emu_io_write(uint16_t addr, uint8_t data) +{ + if((addr & 0xf0) == 0) { + duart_write(addr & 0xf, data); + } +} + +void emu_serin(int port, int c) +{ + duart_serin(port, c); +} diff --git a/emu/src/emu.h b/emu/src/emu.h new file mode 100644 index 0000000..dcded5d --- /dev/null +++ b/emu/src/emu.h @@ -0,0 +1,20 @@ +#ifndef EMU_H_ +#define EMU_H_ + +#include + +int emu_init(void *romimg, int romsz); +void emu_cleanup(void); + +void emu_reset(void); +void emu_step(void); + +uint8_t emu_mem_read(uint16_t addr); +void emu_mem_write(uint16_t addr, uint8_t data); +uint8_t emu_io_read(uint16_t addr); +void emu_io_write(uint16_t addr, uint8_t data); + +void emu_serin(int port, int c); +void emu_serout(int port, int c); /* implemented by the backend */ + +#endif /* EMU_H_ */ diff --git a/emu/src/main.c b/emu/src/main.c new file mode 100644 index 0000000..54a3d3c --- /dev/null +++ b/emu/src/main.c @@ -0,0 +1,149 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "emu.h" + +static void sighandler(int s); +static int parse_args(int argc, char **argv); + +static const char *rom_fname = "rom"; +static const char *termdev = "/dev/tty"; + +static int ttyfd; +static struct termios saved_term; +static volatile int quit; + +int main(int argc, char **argv) +{ + void *rom; + int res, fd, maxfd; + struct stat st; + struct termios term; + fd_set rdset; + struct timeval tv = {0, 0}; + + if(parse_args(argc, argv) == -1) { + return 1; + } + + if((fd = open(rom_fname, O_RDONLY)) == -1) { + fprintf(stderr, "failed to open ROM image: %s: %s\n", rom_fname, strerror(errno)); + return -1; + } + fstat(fd, &st); + + if((rom = mmap(0, st.st_size, PROT_READ, MAP_PRIVATE, fd, 0)) == (void*)-1) { + fprintf(stderr, "failed to map ROM image\n"); + return -1; + } + + if((ttyfd = open(termdev, O_RDWR)) == -1) { + fprintf(stderr, "failed to open terminal device: %s: %s\n", termdev, strerror(errno)); + return -1; + } + if(tcgetattr(ttyfd, &term) == -1) { + perror("failed to get terminal attributes"); + return -1; + } + saved_term = term; + term.c_iflag &= ~(IGNBRK | BRKINT | PARMRK | ISTRIP | INLCR | IGNCR | ICRNL | IXON); + term.c_oflag &= ~OPOST; + term.c_lflag &= ~(ECHO | ECHONL | ICANON | ISIG | IEXTEN); + term.c_cflag = (term.c_cflag & ~(CSIZE | PARENB)) | CS8; + term.c_cc[VMIN] = 0; + term.c_cc[VTIME] = 1; + tcsetattr(ttyfd, TCSAFLUSH, &term); + + if(emu_init(rom, st.st_size) == -1) { + return 1; + } + + signal(SIGINT, sighandler); + signal(SIGQUIT, sighandler); + signal(SIGTERM, sighandler); + signal(SIGSEGV, sighandler); + signal(SIGILL, sighandler); + + while(!quit) { + FD_ZERO(&rdset); + FD_SET(ttyfd, &rdset); + + maxfd = ttyfd; + + res = select(maxfd + 1, &rdset, 0, 0, &tv); + if(quit) break; + + if(res > 0) { + if(FD_ISSET(ttyfd, &rdset)) { + int i, rd; + char buf[256]; + + while((rd = read(ttyfd, buf, sizeof buf)) > 0) { + for(i=0; i" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L CPU:Z80CPU U3 +U 1 1 5EA29512 +P 2000 4050 +F 0 "U3" H 2200 2650 50 0000 C CNN +F 1 "Z80CPU" H 2000 4050 50 0000 C CNN +F 2 "" H 2000 4450 50 0001 C CNN +F 3 "www.zilog.com/manage_directlink.php?filepath=docs/z80/um0080" H 2000 4450 50 0001 C CNN + 1 2000 4050 + 1 0 0 -1 +$EndComp +$Comp +L Memory_EEPROM:28C256 U6 +U 1 1 5EA2C09A +P 3850 4400 +F 0 "U6" H 4000 3350 50 0000 C CNN +F 1 "28C256" V 3850 4400 50 0000 C CNN +F 2 "" H 3850 4400 50 0001 C CNN +F 3 "http://ww1.microchip.com/downloads/en/DeviceDoc/doc0006.pdf" H 3850 4400 50 0001 C CNN + 1 3850 4400 + 1 0 0 -1 +$EndComp +$Comp +L power:GND #PWR08 +U 1 1 5EA2ECD7 +P 2000 5550 +F 0 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2600 7300 50 0001 C CNN + 1 2600 7300 + 1 0 0 -1 +$EndComp +$Comp +L power:VCC #PWR09 +U 1 1 5F4467BC +P 2600 7000 +F 0 "#PWR09" H 2600 6850 50 0001 C CNN +F 1 "VCC" H 2600 7150 50 0000 C CNN +F 2 "" H 2600 7000 50 0001 C CNN +F 3 "" H 2600 7000 50 0001 C CNN + 1 2600 7000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1850 7000 2150 7000 +Connection ~ 2150 7000 +Wire Wire Line + 2150 7000 2450 7000 +Connection ~ 2450 7000 +Wire Wire Line + 2450 7000 2600 7000 +Connection ~ 2600 7000 +Wire Wire Line + 2600 7000 2750 7000 +Connection ~ 2750 7000 +Wire Wire Line + 2750 7000 3050 7000 +Connection ~ 3050 7000 +Wire Wire Line + 3050 7000 3350 7000 +Wire Wire Line + 1850 7300 2150 7300 +Connection ~ 2150 7300 +Wire Wire Line + 2150 7300 2450 7300 +Connection ~ 2450 7300 +Wire Wire Line + 2450 7300 2600 7300 +Connection ~ 2600 7300 +Wire Wire Line + 2600 7300 2750 7300 +Connection ~ 2750 7300 +Wire Wire Line + 2750 7300 3050 7300 +Connection ~ 3050 7300 +Wire Wire Line + 3050 7300 3350 7300 +$Comp +L Device:R R1 +U 1 1 5F463EA2 +P 850 3450 +F 0 "R1" V 950 3450 50 0000 L CNN +F 1 "4.7k" V 850 3350 50 0000 L CNN +F 2 "" V 780 3450 50 0001 C CNN +F 3 "~" H 850 3450 50 0001 C CNN + 1 850 3450 + 0 -1 -1 0 +$EndComp +Connection ~ 700 3450 +Wire Wire Line + 700 3450 700 3550 +Wire Wire Line + 1000 3450 1300 3450 +Text Label 1050 3450 0 50 ~ 0 +~NMI +$Comp +L 74xx:74LS05 U4 +U 2 1 5F4A99C1 +P 7300 6200 +F 0 "U4" H 7300 6050 50 0000 C CNN +F 1 "74LS05" H 7400 6350 50 0000 C CNN +F 2 "" H 7300 6200 50 0001 C CNN +F 3 "http://www.ti.com/lit/gpn/sn74LS05" H 7300 6200 50 0001 C CNN + 2 7300 6200 + -1 0 0 1 +$EndComp +$Comp +L Diode:1N4148 D1 +U 1 1 5F4AD646 +P 8050 6200 +F 0 "D1" H 8050 5984 50 0000 C CNN +F 1 "1N4148" H 8050 6075 50 0000 C CNN +F 2 "Diode_THT:D_DO-35_SOD27_P7.62mm_Horizontal" H 8050 6025 50 0001 C CNN +F 3 "https://assets.nexperia.com/documents/data-sheet/1N4148_1N4448.pdf" H 8050 6200 50 0001 C CNN + 1 8050 6200 + -1 0 0 1 +$EndComp +$Comp +L Device:R R8 +U 1 1 5F4AE323 +P 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+$Comp +L Device:R R6 +U 1 1 5F8611FE +P 2700 1300 +F 0 "R6" H 2750 1350 50 0000 L CNN +F 1 "9.1k" V 2700 1200 50 0000 L CNN +F 2 "" V 2630 1300 50 0001 C CNN +F 3 "~" H 2700 1300 50 0001 C CNN + 1 2700 1300 + 1 0 0 -1 +$EndComp +$Comp +L power:VCC #PWR05 +U 1 1 5F860836 +P 1850 1050 +F 0 "#PWR05" H 1850 900 50 0001 C CNN +F 1 "VCC" H 1867 1223 50 0000 C CNN +F 2 "" H 1850 1050 50 0001 C CNN +F 3 "" H 1850 1050 50 0001 C CNN + 1 1850 1050 + 1 0 0 -1 +$EndComp +$Comp +L power:GND #PWR06 +U 1 1 5F860553 +P 1850 1850 +F 0 "#PWR06" H 1850 1600 50 0001 C CNN +F 1 "GND" H 1855 1677 50 0000 C CNN +F 2 "" H 1850 1850 50 0001 C CNN +F 3 "" H 1850 1850 50 0001 C CNN + 1 1850 1850 + 1 0 0 -1 +$EndComp +$Comp +L Timer:LM555 U2 +U 1 1 5F85DCB5 +P 1850 1450 +F 0 "U2" H 2000 1800 50 0000 C CNN +F 1 "LM555" H 1850 1450 50 0000 C CNN +F 2 "" H 1850 1450 50 0001 C CNN +F 3 "http://www.ti.com/lit/ds/symlink/lm555.pdf" H 1850 1450 50 0001 C CNN + 1 1850 1450 + 1 0 0 -1 +$EndComp +$Comp +L 74xx:74LS05 U4 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0001 C CNN +F 3 "~" H 1200 1700 50 0001 C CNN + 1 1200 1700 + 1 0 0 1 +$EndComp +Wire Wire Line + 1200 1800 1200 1850 +Wire Wire Line + 1200 1850 1850 1850 +Wire Wire Line + 1200 1600 1200 1250 +NoConn ~ 1300 5250 +NoConn ~ 1300 4150 +Wire Wire Line + 1300 3850 1100 3850 +Text Label 1200 3850 0 50 ~ 0 +~M1 +Wire Wire Line + 1300 3950 1100 3950 +Text Label 1100 3950 0 50 ~ 0 +~RFSH +Connection ~ 4700 2600 +Wire Bus Line + 4600 2600 4700 2600 +Wire Bus Line + 4700 2600 6350 2600 +Wire Bus Line + 3150 2600 4700 2600 +Connection ~ 3000 2600 +Wire Wire Line + 3300 2000 3100 2000 +Wire Wire Line + 3300 2100 3100 2100 +Text Label 3200 2000 0 50 ~ 0 +~RD +Text Label 3200 2100 0 50 ~ 0 +~WR +$Comp +L 74xx:74HC14 U1 +U 5 1 5FEF66B9 +P 5600 1300 +F 0 "U1" H 5550 1450 50 0000 L CNN +F 1 "74HC14" H 5550 1150 50 0000 L CNN +F 2 "" H 5600 1300 50 0001 C CNN +F 3 "http://www.ti.com/lit/gpn/sn74HC14" H 5600 1300 50 0001 C CNN + 5 5600 1300 + 1 0 0 -1 +$EndComp +$Comp +L Device:C_Small C9 +U 1 1 5FEF828C +P 5100 1100 +F 0 "C9" H 5008 1054 50 0000 R CNN +F 1 "0.1uF" H 5008 1145 50 0000 R CNN +F 2 "" H 5100 1100 50 0001 C CNN +F 3 "~" H 5100 1100 50 0001 C CNN + 1 5100 1100 + -1 0 0 1 +$EndComp +$Comp +L Device:R R7 +U 1 1 5FF0FBDF +P 4850 1300 +F 0 "R7" V 4750 1250 50 0000 L CNN +F 1 "120R" V 4850 1200 50 0000 L CNN +F 2 "" V 4780 1300 50 0001 C CNN +F 3 "~" H 4850 1300 50 0001 C CNN + 1 4850 1300 + 0 1 1 0 +$EndComp +$Comp +L power:VCC #PWR018 +U 1 1 5FF26567 +P 5100 1000 +F 0 "#PWR018" H 5100 850 50 0001 C CNN +F 1 "VCC" H 5117 1173 50 0000 C CNN +F 2 "" H 5100 1000 50 0001 C CNN +F 3 "" H 5100 1000 50 0001 C CNN + 1 5100 1000 + 1 0 0 -1 +$EndComp +$Comp +L 74xx:74HC14 U1 +U 4 1 5FF485F0 +P 6200 1300 +F 0 "U1" H 6150 1450 50 0000 L CNN +F 1 "74HC14" H 6150 1150 50 0000 L CNN +F 2 "" H 6200 1300 50 0001 C CNN +F 3 "http://www.ti.com/lit/gpn/sn74HC14" H 6200 1300 50 0001 C CNN + 4 6200 1300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6500 1300 6800 1300 +Wire Wire Line + 5000 1300 5100 1300 +Wire Wire Line + 5100 1200 5100 1300 +Wire Bus Line + 6350 2600 6350 3200 +Wire Bus Line + 3000 1100 3000 2600 +Wire Bus Line + 6400 3400 6400 4400 +Wire Bus Line + 4550 3600 4550 5850 +Wire Bus Line + 3000 4650 3000 5850 +Wire Bus Line + 3150 2600 3150 4800 +Wire Bus Line + 4700 2600 4700 4600 +Wire Bus Line + 3000 2600 3000 4250 +Connection ~ 5100 1300 +Wire Wire Line + 5100 1300 5300 1300 +Text Notes 5350 950 0 50 ~ 0 +Delay the UART ~CS~ for a few ns to bring the\ntiming between R/~W~ and ~CS~ within spec\n(this might have been a red herring and not necessary) +$EndSCHEMATC diff --git a/rom/Makefile b/rom/Makefile new file mode 100644 index 0000000..aae4716 --- /dev/null +++ b/rom/Makefile @@ -0,0 +1,25 @@ +src = monitor.asm +obj = $(src:.asm=.o) +bin = monitor + +romtype = 'AT28C256' +romsize = 2048 + +AS = vasmz80_oldstyle +ASFLAGS = -Fvobj +LD = vlink +LDFLAGS = -b rawbin1 + +$(bin): $(obj) + $(LD) -o $@ $(LDFLAGS) -Ttext 0 $(obj) + +%.o: %.asm + $(AS) -o $@ $(ASFLAGS) -L $*.lst $< >/dev/null + +.PHONY: clean +clean: + rm -f $(bin) $(obj) + +.PHONY: program +program: $(bin) + minipro -p 'AT28C256E' -s -w $< diff --git a/rom/monitor.asm b/rom/monitor.asm new file mode 100644 index 0000000..07dcdb4 --- /dev/null +++ b/rom/monitor.asm @@ -0,0 +1,83 @@ +; vi:filetype=z80: + + include "uart.inc" +main: + ld sp, $0 + + ; --- initialize channel A --- + ; reset TX/RX + ld a, UART_CMD_RST_RX + out (UART_REG_CMDA), a + ld a, UART_CMD_RST_TX + out (UART_REG_CMDA), a + ; disable TX/RX + ld a, UART_CMD_TX_OFF | UART_CMD_RX_OFF + out (UART_REG_CMDA), a + ; reset MODEA pointer + ld a, UART_CMD_RST_MPTR + out (UART_REG_CMDA), a + ; set the MODEA register + ld a, UART_M1_8BIT | UART_M1_NOPAR + out (UART_REG_MODEA), a + ld a, UART_M2_STOP1 + out (UART_REG_MODEA), a + ; select baud generator set 1 + xor a + out (UART_REG_AUXCTL), a + ; set the baud rate + ld a, UART_CSEL_TX_9600 | UART_CSEL_RX_9600 + out (UART_REG_CSELA), a + ; enable TX/RX + ld a, UART_CMD_TX_ON | UART_CMD_RX_ON + out (UART_REG_CMDA), a + + ; --- initialize channel B --- + ; reset TX/RX + ld a, UART_CMD_RST_RX + out (UART_REG_CMDB), a + ld a, UART_CMD_RST_TX + out (UART_REG_CMDB), a + ; disable TX/RX + ld a, UART_CMD_TX_OFF | UART_CMD_RX_OFF + out (UART_REG_CMDB), a + ; reset MODEB pointer + ld a, UART_CMD_RST_MPTR + out (UART_REG_CMDB), a + ; write all 0 to MODEB registers to leave OP1 as a general purpose output + xor a + out (UART_REG_MODEB), a + out (UART_REG_MODEB), a + ; set the output port bit 1 + ld a, 2 + out (UART_REG_OSET), a + + ld hl, str_hello + call uart_putstr + ld hl, str_foo + call uart_putstr + +hlt: di + halt + jr hlt + + +uart_putchar: + ld b, a +.wait_txrdy: + in a, (UART_REG_STATA) + bit 2, a ; test status bit 2 (TXRDY) + jr z, .wait_txrdy + ld a, b + out (UART_REG_DATAA), a + ret + +uart_putstr: + ld a, (hl) + cp a, 0 + ret z + call uart_putchar + inc hl + jr uart_putstr + +str_hello asciiz 'The Z80 says hi!',13,10 +str_foo asciiz 'Foobar',13,10 diff --git a/rom/uart.inc b/rom/uart.inc new file mode 100644 index 0000000..ff1868d --- /dev/null +++ b/rom/uart.inc @@ -0,0 +1,91 @@ +; vi:filetype=z80: + +UART_REG_MODEA equ $00 ; MR1A/MR2A +UART_REG_STATA equ $01 ; SRA (rd) +UART_REG_CSELA equ $01 ; CSRA (wr) +UART_REG_CMDA equ $02 ; CRA (wr) +UART_REG_DATAA equ $03 ; RBA (rd) / TBA (wr) + +UART_REG_MODEB equ $08 ; MR1B/MR2B +UART_REG_STATB equ $09 ; SRB (rd) +UART_REG_CSELB equ $09 ; CSRB (wr) +UART_REG_CMDB equ $0a ; CRB (wr) +UART_REG_DATAB equ $0b ; RBB (rd) / TBB (wr) + +UART_REG_IPCR equ $04 ; (rd) +UART_REG_AUXCTL equ $04 ; ACR (wr) +UART_REG_ISTAT equ $05 ; ISR (rd) +UART_REG_IMASK equ $05 ; IMR (wr) +UART_REG_COUNTH equ $06 ; CUR (rd) +UART_REG_COUNTL equ $07 ; CLR (rd) +UART_REG_CTSETH equ $06 ; CTUR (wr) +UART_REG_CTSETL equ $07 ; CTLR (wr) + +UART_REG_IVEC equ $0c ; IVR +UART_REG_IPORT equ $0d ; (rd) +UART_REG_OPCR equ $0d ; (wr) +UART_REG_CSTART_CMD equ $0e ; (rd) +UART_REG_CSTOP_CMD equ $0f ; (rd) +UART_REG_OSET equ $0e ; (wr) +UART_REG_OCLR equ $0f ; (wr) + + +UART_M1_5BIT equ $00 +UART_M1_6BIT equ $01 +UART_M1_7BIT equ $02 +UART_M1_8BIT equ $03 +UART_M1_PAREVEN equ $00 +UART_M1_PARODD equ $04 +UART_M1_NOPAR equ $10 +UART_M1_IRQ_RDY equ $00 +UART_M1_IRQ_FULL equ $40 +UART_M1_RX_RTS equ $80 + +; stop bit count goes in low nibble of MODE2 register +UART_M2_STOP1 equ $07 +UART_M2_CTS equ $10 +UART_M2_TX_RTS equ $20 +UART_M2_ECHO equ $40 +UART_M2_LOOP_LOCAL equ $80 +UART_M2_LOOP_REMOTE equ $c0 + +UART_CSEL_TX_300 equ $04 +UART_CSEL_RX_300 equ $40 +UART_CSEL_TX_9600 equ $0b +UART_CSEL_RX_9600 equ $b0 +UART_CSEL_TX_38400_19200 equ $0c +UART_CSEL_RX_38400_19200 equ $c0 +UART_CSEL_TX_TIMER equ $0d +UART_CSEL_RX_TIMER equ $d0 + +UART_STAT_RXRDY equ $01 +UART_STAT_FFULL equ $02 +UART_STAT_TXRDY equ $04 +UART_STAT_TXEMPTY equ $08 +UART_STAT_ERR_OVR equ $10 +UART_STAT_ERR_PAR equ $20 +UART_STAT_ERR_FRM equ $40 +UART_STAT_ERR_BRK equ $80 + +UART_CMD_RX_ON equ $01 +UART_CMD_RX_OFF equ $02 +UART_CMD_TX_ON equ $04 +UART_CMD_TX_OFF equ $08 +UART_CMD_RST_MPTR equ $10 +UART_CMD_RST_RX equ $20 +UART_CMD_RST_TX equ $30 +UART_CMD_RST_ERR equ $40 +UART_CMD_RST_BRKINT equ $50 +UART_CMD_START_BRK equ $60 +UART_CMD_STOP_BRK equ $70 + +UART_OPCR_OP2_TXCA16 equ $01 +UART_OPCR_OP2_TXA equ $02 +UART_OPCR_OP2_RXA equ $03 +UART_OPCR_OP3_CTR equ $04 +UART_OPCR_OP3_TXB equ $08 +UART_OPCR_OP3_RXB equ $0c +UART_OPCR_OP4_RXRDYA equ $10 +UART_OPCR_OP5_RXRDYB equ $20 +UART_OPCR_OP6_TXRDYA equ $40 +UART_OPCR_OP7_TXRDYB equ $80 diff --git a/sym-lib-table b/sym-lib-table deleted file mode 100644 index 17d264b..0000000 --- a/sym-lib-table +++ /dev/null @@ -1,3 +0,0 @@ -(sym_lib_table - (lib (name z80comp2)(type Legacy)(uri ${KIPRJMOD}/z80comp2.lib)(options "")(descr "")) -) diff --git a/z80comp2-cache.lib b/z80comp2-cache.lib deleted file mode 100644 index 1b03780..0000000 --- a/z80comp2-cache.lib +++ /dev/null @@ -1,594 +0,0 @@ -EESchema-LIBRARY Version 2.4 -#encoding utf-8 -# -# 74xx_74HC14 -# -DEF 74xx_74HC14 U 0 40 Y Y 7 L N -F0 "U" 0 50 50 H V C CNN -F1 "74xx_74HC14" 0 -50 50 H V C CNN -F2 "" 0 0 50 H I C CNN -F3 "" 0 0 50 H I C CNN -ALIAS 74LS14 -$FPLIST - DIP*W7.62mm* -$ENDFPLIST -DRAW -S -200 300 200 -300 7 1 10 f -P 4 1 0 10 -150 150 -150 -150 150 0 -150 150 f -P 4 2 0 10 -150 150 -150 -150 150 0 -150 150 f -P 4 3 0 10 -150 150 -150 -150 150 0 -150 150 f -P 4 4 0 10 -150 150 -150 -150 150 0 -150 150 f -P 4 5 0 10 -150 150 -150 -150 150 0 -150 150 f -P 4 6 0 10 -150 150 -150 -150 150 0 -150 150 f -P 3 1 1 0 -75 -50 -75 50 -25 50 N -P 4 1 1 0 -100 -50 -25 -50 -25 50 0 50 N -P 3 2 1 0 -75 -50 -75 50 -25 50 N -P 4 2 1 0 -100 -50 -25 -50 -25 50 0 50 N -P 3 3 1 0 -75 -50 -75 50 -25 50 N -P 4 3 1 0 -100 -50 -25 -50 -25 50 0 50 N -P 3 4 1 0 -75 -50 -75 50 -25 50 N -P 4 4 1 0 -100 -50 -25 -50 -25 50 0 50 N -P 3 5 1 0 -75 -50 -75 50 -25 50 N -P 4 5 1 0 -100 -50 -25 -50 -25 50 0 50 N -P 3 6 1 0 -75 -50 -75 50 -25 50 N -P 4 6 1 0 -100 -50 -25 -50 -25 50 0 50 N -X ~ 1 -300 0 150 R 50 50 1 0 I -X ~ 2 300 0 150 L 50 50 1 0 O I -X ~ 3 -300 0 150 R 50 50 2 0 I -X ~ 4 300 0 150 L 50 50 2 0 O I -X ~ 5 -300 0 150 R 50 50 3 0 I -X ~ 6 300 0 150 L 50 50 3 0 O I -X ~ 8 300 0 150 L 50 50 4 0 O I -X ~ 9 -300 0 150 R 50 50 4 0 I -X ~ 10 300 0 150 L 50 50 5 0 O I -X ~ 11 -300 0 150 R 50 50 5 0 I -X ~ 12 300 0 150 L 50 50 6 0 O I -X ~ 13 -300 0 150 R 50 50 6 0 I -X VCC 14 0 500 200 D 50 50 7 0 W -X GND 7 0 -500 200 U 50 50 7 0 W -ENDDRAW -ENDDEF -# -# 74xx_74LS05 -# -DEF 74xx_74LS05 U 0 40 Y Y 7 L N -F0 "U" 0 50 50 H V C CNN -F1 "74xx_74LS05" 0 -50 50 H V C CNN -F2 "" 0 0 50 H I C CNN -F3 "" 0 0 50 H I C CNN -ALIAS 74LS06 74LS06N -$FPLIST - DIP*W7.62mm* -$ENDFPLIST -DRAW -S -200 300 200 -300 7 1 10 f -P 4 1 0 10 -150 150 -150 -150 150 0 -150 150 f -P 4 2 0 10 -150 150 -150 -150 150 0 -150 150 f -P 4 3 0 10 -150 150 -150 -150 150 0 -150 150 f -P 4 4 0 10 -150 150 -150 -150 150 0 -150 150 f -P 4 5 0 10 -150 150 -150 -150 150 0 -150 150 f -P 4 6 0 10 -150 150 -150 -150 150 0 -150 150 f -X ~ 1 -300 0 150 R 50 50 1 0 I -X ~ 2 300 0 150 L 50 50 1 0 C I -X ~ 3 -300 0 150 R 50 50 2 0 I -X ~ 4 300 0 150 L 50 50 2 0 C I -X ~ 5 -300 0 150 R 50 50 3 0 I -X ~ 6 300 0 150 L 50 50 3 0 C I -X ~ 8 300 0 150 L 50 50 4 0 C I -X ~ 9 -300 0 150 R 50 50 4 0 I -X ~ 10 300 0 150 L 50 50 5 0 C I -X ~ 11 -300 0 150 R 50 50 5 0 I -X ~ 12 300 0 150 L 50 50 6 0 C I -X ~ 13 -300 0 150 R 50 50 6 0 I -X VCC 14 0 500 200 D 50 50 7 0 W -X GND 7 0 -500 200 U 50 50 7 0 W -ENDDRAW -ENDDEF -# -# CPU_Z80CPU -# -DEF CPU_Z80CPU U 0 40 Y Y 1 F N -F0 "U" -550 1400 50 H V L CNN -F1 "CPU_Z80CPU" 250 1400 50 H V L CNN -F2 "" 0 400 50 H I C CNN -F3 "" 0 400 50 H I C CNN -$FPLIST - DIP* - PDIP* -$ENDFPLIST -DRAW -S -550 1350 550 -1350 0 1 10 f -X A11 1 700 100 150 L 50 50 1 1 O -X D6 10 700 -1100 150 L 50 50 1 1 B -X VCC 11 0 1500 150 D 50 50 1 1 W -X D2 12 700 -700 150 L 50 50 1 1 B -X D7 13 700 -1200 150 L 50 50 1 1 B -X D0 14 700 -500 150 L 50 50 1 1 B -X D1 15 700 -600 150 L 50 50 1 1 B -X ~INT~ 16 -700 500 150 R 50 50 1 1 I -X ~NMI~ 17 -700 600 150 R 50 50 1 1 I -X ~HALT~ 18 -700 -100 150 R 50 50 1 1 O -X ~MREQ~ 19 -700 -700 150 R 50 50 1 1 O -X A12 2 700 0 150 L 50 50 1 1 O -X ~IORQ~ 20 -700 -800 150 R 50 50 1 1 O -X ~RD~ 21 -700 -500 150 R 50 50 1 1 O -X ~WR~ 22 -700 -600 150 R 50 50 1 1 O -X ~BUSACK~ 23 -700 -1200 150 R 50 50 1 1 O -X ~WAIT~ 24 -700 0 150 R 50 50 1 1 I -X ~BUSRQ~ 25 -700 -1100 150 R 50 50 1 1 I -X ~RESET~ 26 -700 1200 150 R 50 50 1 1 I -X ~M1~ 27 -700 200 150 R 50 50 1 1 O -X ~RFSH~ 28 -700 100 150 R 50 50 1 1 O -X GND 29 0 -1500 150 U 50 50 1 1 W -X A13 3 700 -100 150 L 50 50 1 1 O -X A0 30 700 1200 150 L 50 50 1 1 O -X A1 31 700 1100 150 L 50 50 1 1 O -X A2 32 700 1000 150 L 50 50 1 1 O -X A3 33 700 900 150 L 50 50 1 1 O -X A4 34 700 800 150 L 50 50 1 1 O -X A5 35 700 700 150 L 50 50 1 1 O -X A6 36 700 600 150 L 50 50 1 1 O -X A7 37 700 500 150 L 50 50 1 1 O -X A8 38 700 400 150 L 50 50 1 1 O -X A9 39 700 300 150 L 50 50 1 1 O -X A14 4 700 -200 150 L 50 50 1 1 O -X A10 40 700 200 150 L 50 50 1 1 O -X A15 5 700 -300 150 L 50 50 1 1 O -X ~CLK~ 6 -700 900 150 R 50 50 1 1 I C -X D4 7 700 -900 150 L 50 50 1 1 B -X D3 8 700 -800 150 L 50 50 1 1 B -X D5 9 700 -1000 150 L 50 50 1 1 B -ENDDRAW -ENDDEF -# -# Connector_Conn_01x03_Male -# -DEF Connector_Conn_01x03_Male J 0 40 Y N 1 F N -F0 "J" 0 200 50 H V C CNN -F1 "Connector_Conn_01x03_Male" 0 -200 50 H V C CNN -F2 "" 0 0 50 H I C CNN -F3 "" 0 0 50 H I C CNN -$FPLIST - Connector*:*_1x??_* -$ENDFPLIST -DRAW -S 34 -95 0 -105 1 1 6 F -S 34 5 0 -5 1 1 6 F -S 34 105 0 95 1 1 6 F -P 2 1 1 6 50 -100 34 -100 N -P 2 1 1 6 50 0 34 0 N -P 2 1 1 6 50 100 34 100 N -X Pin_1 1 200 100 150 L 50 50 1 1 P -X Pin_2 2 200 0 150 L 50 50 1 1 P -X Pin_3 3 200 -100 150 L 50 50 1 1 P -ENDDRAW -ENDDEF -# -# Connector_DB9_Male -# -DEF Connector_DB9_Male J 0 40 Y N 1 F N -F0 "J" 0 550 50 H V C CNN -F1 "Connector_DB9_Male" 0 -575 50 H V C CNN -F2 "" 0 0 50 H I C CNN -F3 "" 0 0 50 H I C CNN -$FPLIST - DSUB*Male* -$ENDFPLIST -DRAW -C -70 -400 30 0 1 0 F -C -70 -200 30 0 1 0 F -C -70 0 30 0 1 0 F -C -70 200 30 0 1 0 F -C -70 400 30 0 1 0 F -C 50 -300 30 0 1 0 F -C 50 -100 30 0 1 0 F -C 50 100 30 0 1 0 F -C 50 300 30 0 1 0 F -P 2 0 1 0 -150 -400 -100 -400 N -P 2 0 1 0 -150 -300 20 -300 N -P 2 0 1 0 -150 -200 -100 -200 N -P 2 0 1 0 -150 -100 20 -100 N -P 2 0 1 0 -150 0 -100 0 N -P 2 0 1 0 -150 100 20 100 N -P 2 0 1 0 -150 200 -100 200 N -P 2 0 1 0 -150 300 20 300 N -P 2 0 1 0 -150 400 -100 400 N -P 5 0 1 10 -150 -525 -150 525 150 375 150 -375 -150 -525 f -X 1 1 -300 -400 150 R 50 50 1 1 P -X 2 2 -300 -200 150 R 50 50 1 1 P -X 3 3 -300 0 150 R 50 50 1 1 P -X 4 4 -300 200 150 R 50 50 1 1 P -X 5 5 -300 400 150 R 50 50 1 1 P -X 6 6 -300 -300 150 R 50 50 1 1 P -X 7 7 -300 -100 150 R 50 50 1 1 P -X 8 8 -300 100 150 R 50 50 1 1 P -X 9 9 -300 300 150 R 50 50 1 1 P -ENDDRAW -ENDDEF -# -# Device_C -# -DEF Device_C C 0 10 N Y 1 F N -F0 "C" 25 100 50 H V L CNN -F1 "Device_C" 25 -100 50 H V L CNN -F2 "" 38 -150 50 H I C CNN -F3 "" 0 0 50 H I C CNN -$FPLIST - C_* -$ENDFPLIST -DRAW -P 2 0 1 20 -80 -30 80 -30 N -P 2 0 1 20 -80 30 80 30 N -X ~ 1 0 150 110 D 50 50 1 1 P -X ~ 2 0 -150 110 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# Device_C_Small -# -DEF Device_C_Small C 0 10 N N 1 F N -F0 "C" 10 70 50 H V L CNN -F1 "Device_C_Small" 10 -80 50 H V L CNN -F2 "" 0 0 50 H I C CNN -F3 "" 0 0 50 H I C CNN -$FPLIST - C_* -$ENDFPLIST -DRAW -P 2 0 1 13 -60 -20 60 -20 N -P 2 0 1 12 -60 20 60 20 N -X ~ 1 0 100 80 D 50 50 1 1 P -X ~ 2 0 -100 80 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# Device_Crystal_Small -# -DEF Device_Crystal_Small Y 0 40 N N 1 F N -F0 "Y" 0 100 50 H V C CNN -F1 "Device_Crystal_Small" 0 -100 50 H V C CNN -F2 "" 0 0 50 H I C CNN -F3 "" 0 0 50 H I C CNN -$FPLIST - Crystal* -$ENDFPLIST -DRAW -S -30 -60 30 60 0 1 0 N -P 2 0 1 15 -50 -30 -50 30 N -P 2 0 1 15 50 -30 50 30 N -X 1 1 -100 0 50 R 50 50 1 1 P -X 2 2 100 0 50 L 50 50 1 1 P -ENDDRAW -ENDDEF -# -# Device_R -# -DEF Device_R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "Device_R" 0 0 50 V V C CNN -F2 "" -70 0 50 V I C CNN -F3 "" 0 0 50 H I C CNN -$FPLIST - R_* -$ENDFPLIST -DRAW -S -40 -100 40 100 0 1 10 N -X ~ 1 0 150 50 D 50 50 1 1 P -X ~ 2 0 -150 50 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# Diode_1N4148 -# -DEF Diode_1N4148 D 0 40 N N 1 F N -F0 "D" 0 100 50 H V C CNN -F1 "Diode_1N4148" 0 -100 50 H V C CNN -F2 "Diode_THT:D_DO-35_SOD27_P7.62mm_Horizontal" 0 -175 50 H I C CNN -F3 "" 0 0 50 H I C CNN -ALIAS 1N4448 1N4149 1N4151 1N914 BA243 BA244 BA282 BA283 BAV17 BAV18 BAV19 BAV20 BAV21 BAW75 BAW76 BAY93 -$FPLIST - D*DO?35* -$ENDFPLIST -DRAW -P 2 0 1 8 -50 50 -50 -50 N -P 2 0 1 0 50 0 -50 0 N -P 4 0 1 8 50 50 50 -50 -50 0 50 50 N -X K 1 -150 0 100 R 50 50 1 1 P -X A 2 150 0 100 L 50 50 1 1 P -ENDDRAW -ENDDEF -# -# Interface_UART_MAX232 -# -DEF Interface_UART_MAX232 U 0 40 Y Y 1 F N -F0 "U" -100 1125 50 H V R CNN -F1 "Interface_UART_MAX232" -100 1050 50 H V R CNN -F2 "" 50 -1050 50 H I L CNN -F3 "" 0 100 50 H I C CNN -ALIAS MAX232I MAX202 ADM232A MAX3232 ICL3232 -$FPLIST - SOIC*P1.27mm* - DIP*W7.62mm* - TSSOP*4.4x5mm*P0.65mm* -$ENDFPLIST -DRAW -C -100 -700 25 0 1 10 N -C -100 -500 25 0 1 10 N -C 25 -300 25 0 1 10 N -C 25 -100 25 0 1 10 N -T 0 -450 -900 50 0 0 0 LOGIC Normal 0 C C -T 0 450 -900 50 0 0 0 RS232 Normal 0 C C -S -600 -1000 600 1000 0 1 10 f -P 2 0 1 10 -150 -300 -325 -300 N -P 2 0 1 10 -150 -100 -325 -100 N -P 2 0 1 10 -125 -700 -325 -700 N -P 2 0 1 10 -125 -500 -325 -500 N -P 2 0 1 10 50 -300 250 -300 N -P 2 0 1 10 50 -100 250 -100 N -P 2 0 1 10 75 -700 250 -700 N -P 2 0 1 10 75 -500 250 -500 N -P 4 0 1 10 -150 -225 -150 -375 0 -300 -150 -225 N -P 4 0 1 10 -150 -25 -150 -175 0 -100 -150 -25 N -P 4 0 1 10 75 -625 75 -775 -75 -700 75 -625 N -P 4 0 1 10 75 -425 75 -575 -75 -500 75 -425 N -X C1+ 1 -800 900 200 R 50 50 1 1 P -X T2IN 10 -800 -300 200 R 50 50 1 1 I -X T1IN 11 -800 -100 200 R 50 50 1 1 I -X R1OUT 12 -800 -500 200 R 50 50 1 1 O -X R1IN 13 800 -500 200 L 50 50 1 1 I -X T1OUT 14 800 -100 200 L 50 50 1 1 O -X GND 15 0 -1200 200 U 50 50 1 1 W -X VCC 16 0 1200 200 D 50 50 1 1 W -X VS+ 2 800 400 200 L 50 50 1 1 w -X C1- 3 -800 600 200 R 50 50 1 1 P -X C2+ 4 800 900 200 L 50 50 1 1 P -X C2- 5 800 600 200 L 50 50 1 1 P -X VS- 6 800 100 200 L 50 50 1 1 w -X T2OUT 7 800 -300 200 L 50 50 1 1 O -X R2IN 8 800 -700 200 L 50 50 1 1 I -X R2OUT 9 -800 -700 200 R 50 50 1 1 O -ENDDRAW -ENDDEF -# -# Memory_EEPROM_28C256 -# -DEF Memory_EEPROM_28C256 U 0 20 Y Y 1 F N -F0 "U" -300 1050 50 H V C CNN -F1 "Memory_EEPROM_28C256" 100 -1050 50 H V L CNN -F2 "" 0 0 50 H I C CNN -F3 "" 0 0 50 H I C CNN -$FPLIST - DIP*W15.24mm* - SOIC*7.5x17.9mm*P1.27mm* -$ENDFPLIST -DRAW -S -300 1000 300 -1000 1 1 10 f -X A14 1 -400 -500 100 R 50 50 1 1 I -X A0 10 -400 900 100 R 50 50 1 1 I -X D0 11 400 900 100 L 50 50 1 1 T -X D1 12 400 800 100 L 50 50 1 1 T -X D2 13 400 700 100 L 50 50 1 1 T -X GND 14 0 -1100 100 U 50 50 1 1 W -X D3 15 400 600 100 L 50 50 1 1 T -X D4 16 400 500 100 L 50 50 1 1 T -X D5 17 400 400 100 L 50 50 1 1 T -X D6 18 400 300 100 L 50 50 1 1 T -X D7 19 400 200 100 L 50 50 1 1 T -X A12 2 -400 -300 100 R 50 50 1 1 I -X ~CS 20 -400 -900 100 R 50 50 1 1 I -X A10 21 -400 -100 100 R 50 50 1 1 I -X ~OE 22 -400 -800 100 R 50 50 1 1 I -X A11 23 -400 -200 100 R 50 50 1 1 I -X A9 24 -400 0 100 R 50 50 1 1 I -X A8 25 -400 100 100 R 50 50 1 1 I -X A13 26 -400 -400 100 R 50 50 1 1 I -X ~WE 27 -400 -700 100 R 50 50 1 1 I -X VCC 28 0 1100 100 D 50 50 1 1 W -X A7 3 -400 200 100 R 50 50 1 1 I -X A6 4 -400 300 100 R 50 50 1 1 I -X A5 5 -400 400 100 R 50 50 1 1 I -X A4 6 -400 500 100 R 50 50 1 1 I -X A3 7 -400 600 100 R 50 50 1 1 I -X A2 8 -400 700 100 R 50 50 1 1 I -X A1 9 -400 800 100 R 50 50 1 1 I -ENDDRAW -ENDDEF -# -# Switch_SW_Push -# -DEF Switch_SW_Push SW 0 40 N N 1 F N -F0 "SW" 50 100 50 H V L CNN -F1 "Switch_SW_Push" 0 -60 50 H V C CNN -F2 "" 0 200 50 H I C CNN -F3 "" 0 200 50 H I C CNN -DRAW -C -80 0 20 0 1 0 N -C 80 0 20 0 1 0 N -P 2 0 1 0 0 50 0 120 N -P 2 0 1 0 100 50 -100 50 N -X 1 1 -200 0 100 R 50 50 0 1 P -X 2 2 200 0 100 L 50 50 0 1 P -ENDDRAW -ENDDEF -# -# Timer_LM555 -# -DEF Timer_LM555 U 0 20 Y Y 1 F N -F0 "U" -400 350 50 H V L CNN -F1 "Timer_LM555" 100 350 50 H V L CNN -F2 "" 0 0 50 H I C CNN -F3 "" 0 0 50 H I C CNN -ALIAS ICM7555 LMC555xM LMC555xMM LMC555xN MC1455 TLC555CD TLC555CP TLC555CPS NA555 NE555 SE555 SA555 -$FPLIST - SOIC*3.9x4.9mm*P1.27mm* - DIP*W7.62mm* - TSSOP*3x3mm*P0.65mm* -$ENDFPLIST -DRAW -S -350 -300 350 300 0 1 10 f -S -350 -300 350 300 0 1 10 f -X GND 1 0 -400 100 U 50 50 0 0 W -X VCC 8 0 400 100 D 50 50 0 0 W -X TR 2 -500 200 150 R 50 50 1 1 I -X Q 3 500 200 150 L 50 50 1 1 O -X R 4 -500 -200 150 R 50 50 1 1 I I -X CV 5 -500 0 150 R 50 50 1 1 I -X THR 6 500 -200 150 L 50 50 1 1 I -X DIS 7 500 0 150 L 50 50 1 1 I -ENDDRAW -ENDDEF -# -# power_GND -# -DEF power_GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 -250 50 H I C CNN -F1 "power_GND" 0 -150 50 H V C CNN -F2 "" 0 0 50 H I C CNN -F3 "" 0 0 50 H I C CNN -DRAW -P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N -X GND 1 0 0 0 D 50 50 1 1 W N -ENDDRAW -ENDDEF -# -# power_VCC -# -DEF power_VCC #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 -150 50 H I C CNN -F1 "power_VCC" 0 150 50 H V C CNN -F2 "" 0 0 50 H I C CNN -F3 "" 0 0 50 H I C CNN -DRAW -C 0 75 25 0 1 0 N -P 2 0 1 0 0 0 0 50 N -X VCC 1 0 0 0 U 50 50 1 1 W N -ENDDRAW -ENDDEF -# -# z80comp2_mc68681 -# -DEF z80comp2_mc68681 U 0 40 Y Y 1 F N -F0 "U" 150 1350 50 H V C CNN -F1 "z80comp2_mc68681" -250 1350 50 H V C CNN -F2 "" 550 -550 50 H I C CNN -F3 "" 550 -550 50 H I C CNN -DRAW -S -350 1300 350 -1500 0 1 0 f -X RS1 1 -550 900 200 R 50 50 1 1 I -X RXDB 10 550 -650 200 L 50 50 1 1 P -X TXDB 11 550 -750 200 L 50 50 1 1 P -X OP1 12 550 400 200 L 50 50 1 1 O -X OP3 13 550 200 200 L 50 50 1 1 O -X OP5 14 550 0 200 L 50 50 1 1 O -X OP7 15 550 -200 200 L 50 50 1 1 O -X D1 16 -550 300 200 R 50 50 1 1 B -X D3 17 -550 100 200 R 50 50 1 1 B -X D5 18 -550 -100 200 R 50 50 1 1 B -X D7 19 -550 -300 200 R 50 50 1 1 B -X IP3 2 550 900 200 L 50 50 1 1 I -X GND 20 0 -1700 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07:44:53 -version=1 -last_client=kicad -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir= -[eeschema/libraries] diff --git a/z80comp2.sch b/z80comp2.sch deleted file mode 100644 index 9c74d01..0000000 --- a/z80comp2.sch +++ /dev/null @@ -1,1741 +0,0 @@ -EESchema Schematic File Version 4 -EELAYER 30 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "Z80 computer 2" -Date "2020-04-29" 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0001 C CNN - 1 7750 6050 - 1 0 0 1 -$EndComp -$Comp -L power:VCC #PWR023 -U 1 1 5F4B4193 -P 7750 5900 -F 0 "#PWR023" H 7750 5750 50 0001 C CNN -F 1 "VCC" H 7767 6073 50 0000 C CNN -F 2 "" H 7750 5900 50 0001 C CNN -F 3 "" H 7750 5900 50 0001 C CNN - 1 7750 5900 - 1 0 0 -1 -$EndComp -Wire Wire Line - 7900 5250 7900 6200 -Connection ~ 7900 6200 -Wire Wire Line - 8200 6200 8500 6200 -Text Label 8200 6200 0 50 ~ 0 -UARTEN -Wire Wire Line - 7600 6200 7750 6200 -Connection ~ 7750 6200 -Wire Wire Line - 7750 6200 7900 6200 -Wire Wire Line - 7000 6200 850 6200 -Wire Wire Line - 850 6200 850 4250 -Wire Wire Line - 850 4250 1000 4250 -Wire Wire Line - 1000 4250 1000 4050 -Connection ~ 1000 4050 -Wire Wire Line - 4400 1200 4700 1200 -Text Label 4400 1200 0 50 ~ 0 -UARTEN -Wire Wire Line - 7900 5150 8050 5150 -Text Label 7900 5150 0 50 ~ 0 -~INT -Wire Wire Line - 8300 4950 8350 4950 -Text Notes 3950 2300 0 50 ~ 0 -GAL16V8: glue.pld -$Comp -L power:VCC #PWR04 -U 1 1 5F6A583C -P 1300 5150 -F 0 "#PWR04" H 1300 5000 50 0001 C CNN -F 1 "VCC" H 1317 5323 50 0000 C CNN -F 2 "" H 1300 5150 50 0001 C CNN -F 3 "" H 1300 5150 50 0001 C CNN - 1 1300 5150 - 1 0 0 -1 -$EndComp -Wire Wire Line - 3300 1600 3100 1600 -Text Label 3200 1600 0 50 ~ 0 -~M1 -Wire Wire Line - 3300 1900 3100 1900 -Text Label 3100 1900 0 50 ~ 0 -~RFSH -Wire Wire Line - 4400 1700 4700 1700 -Text Label 4400 1700 0 50 ~ 0 -~IACK -Wire Wire Line - 6800 4700 6600 4700 -Text Label 6600 4700 0 50 ~ 0 -~IACK -$Comp -L 74xx:74HC14 U1 -U 6 1 5F7B3414 -P 850 2400 -F 0 "U1" V 650 2400 50 0000 L CNN -F 1 "74HC14" H 850 2250 50 0000 L CNN -F 2 "" H 850 2400 50 0001 C CNN -F 3 "http://www.ti.com/lit/gpn/sn74HC14" H 850 2400 50 0001 C CNN - 6 850 2400 - 0 1 1 0 -$EndComp -Wire Wire Line - 850 2700 850 3150 -Wire Wire Line - 850 3150 1300 3150 -Wire Wire Line - 850 2100 850 1850 -Text Label 850 2050 1 50 ~ 0 -UCLK -Wire Wire Line - 1300 1650 1350 1650 -$Comp -L power:VCC #PWR03 -U 1 1 5F97FBA6 -P 1300 1650 -F 0 "#PWR03" H 1300 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50 0000 L CNN -F 2 "" V 1130 1100 50 0001 C CNN -F 3 "~" H 1200 1100 50 0001 C CNN - 1 1200 1100 - 1 0 0 -1 -$EndComp -NoConn ~ 1350 1450 -$Comp -L power:VCC #PWR011 -U 1 1 5F8CF8A4 -P 2700 1150 -F 0 "#PWR011" H 2700 1000 50 0001 C CNN -F 1 "VCC" H 2717 1323 50 0000 C CNN -F 2 "" H 2700 1150 50 0001 C CNN -F 3 "" H 2700 1150 50 0001 C CNN - 1 2700 1150 - 1 0 0 -1 -$EndComp -Text Label 2350 1250 0 50 ~ 0 -RST -Wire Wire Line - 2350 1250 2550 1250 -Wire Wire Line - 2700 1850 1850 1850 -Wire Wire Line - 2350 1650 2700 1650 -Connection ~ 2700 1450 -Wire Wire Line - 2700 1450 2700 1650 -$Comp -L Device:C_Small C5 -U 1 1 5F880397 -P 2700 1750 -F 0 "C5" H 2609 1704 50 0000 R CNN -F 1 "0.1uF" H 2609 1795 50 0000 R CNN -F 2 "" H 2700 1750 50 0001 C CNN -F 3 "~" H 2700 1750 50 0001 C CNN - 1 2700 1750 - 1 0 0 1 -$EndComp -Wire Wire Line - 2350 1450 2700 1450 -$Comp -L Device:R R6 -U 1 1 5F8611FE -P 2700 1300 -F 0 "R6" H 2750 1350 50 0000 L CNN -F 1 "9.1k" V 2700 1200 50 0000 L CNN -F 2 "" V 2630 1300 50 0001 C CNN -F 3 "~" H 2700 1300 50 0001 C CNN - 1 2700 1300 - 1 0 0 -1 -$EndComp -$Comp -L power:VCC #PWR05 -U 1 1 5F860836 -P 1850 1050 -F 0 "#PWR05" H 1850 900 50 0001 C CNN -F 1 "VCC" H 1867 1223 50 0000 C CNN -F 2 "" H 1850 1050 50 0001 C CNN -F 3 "" H 1850 1050 50 0001 C CNN - 1 1850 1050 - 1 0 0 -1 -$EndComp -$Comp -L power:GND #PWR06 -U 1 1 5F860553 -P 1850 1850 -F 0 "#PWR06" H 1850 1600 50 0001 C CNN -F 1 "GND" H 1855 1677 50 0000 C CNN -F 2 "" H 1850 1850 50 0001 C CNN -F 3 "" H 1850 1850 50 0001 C CNN - 1 1850 1850 - 1 0 0 -1 -$EndComp -$Comp -L Timer:LM555 U2 -U 1 1 5F85DCB5 -P 1850 1450 -F 0 "U2" H 2000 1800 50 0000 C CNN -F 1 "LM555" H 1850 1450 50 0000 C CNN -F 2 "" H 1850 1450 50 0001 C CNN -F 3 "http://www.ti.com/lit/ds/symlink/lm555.pdf" H 1850 1450 50 0001 C CNN - 1 1850 1450 - 1 0 0 -1 -$EndComp -$Comp -L 74xx:74LS05 U4 -U 1 1 5F9CB042 -P 2450 800 -F 0 "U4" H 2450 650 50 0000 C CNN -F 1 "74LS05" H 2550 950 50 0000 C CNN -F 2 "" H 2450 800 50 0001 C CNN -F 3 "http://www.ti.com/lit/gpn/sn74LS05" H 2450 800 50 0001 C CNN - 1 2450 800 - 1 0 0 -1 -$EndComp -Wire Wire Line - 2150 800 2150 1050 -Wire Wire Line - 2150 1050 2550 1050 -Wire Wire Line - 2550 1050 2550 1250 -Text Label 2850 800 0 50 ~ 0 -~RST -$Comp -L Device:R R4 -U 1 1 5FA0761C -P 1050 2700 -F 0 "R4" H 1120 2746 50 0000 L CNN -F 1 "4.7k" V 1050 2600 50 0000 L CNN -F 2 "" V 980 2700 50 0001 C CNN -F 3 "~" H 1050 2700 50 0001 C CNN - 1 1050 2700 - 1 0 0 -1 -$EndComp -Text Notes 1350 700 0 50 ~ 0 -Power-on reset -Wire Wire Line - 2750 800 3000 800 -Wire Wire Line - 1050 2850 1300 2850 -Wire Wire Line - 1050 2550 2000 2550 -Connection ~ 2000 2550 -Connection ~ 2700 1650 -Connection ~ 1850 1850 -$Comp -L Device:C_Small C1 -U 1 1 5FC80F1C -P 1200 1700 -F 0 "C1" H 1109 1654 50 0000 R CNN -F 1 "0.1uF" H 1109 1745 50 0000 R CNN -F 2 "" H 1200 1700 50 0001 C CNN -F 3 "~" H 1200 1700 50 0001 C CNN - 1 1200 1700 - 1 0 0 1 -$EndComp -Wire Wire Line - 1200 1800 1200 1850 -Wire Wire Line - 1200 1850 1850 1850 -Wire Wire Line - 1200 1600 1200 1250 -NoConn ~ 1300 5250 -NoConn ~ 1300 4150 -Wire Wire Line - 1300 3850 1100 3850 -Text Label 1200 3850 0 50 ~ 0 -~M1 -Wire Wire Line - 1300 3950 1100 3950 -Text Label 1100 3950 0 50 ~ 0 -~RFSH -Connection ~ 4700 2600 -Wire Bus Line - 4600 2600 4700 2600 -Wire Bus Line - 4700 2600 6350 2600 -Wire Bus Line - 3150 2600 4700 2600 -Connection ~ 3000 2600 -Wire Wire Line - 3300 2000 3100 2000 -Wire Wire Line - 3300 2100 3100 2100 -Text Label 3200 2000 0 50 ~ 0 -~RD -Text Label 3200 2100 0 50 ~ 0 -~WR -$Comp -L 74xx:74HC14 U1 -U 5 1 5FEF66B9 -P 5600 1300 -F 0 "U1" H 5550 1450 50 0000 L CNN -F 1 "74HC14" H 5550 1150 50 0000 L CNN -F 2 "" H 5600 1300 50 0001 C CNN -F 3 "http://www.ti.com/lit/gpn/sn74HC14" H 5600 1300 50 0001 C CNN - 5 5600 1300 - 1 0 0 -1 -$EndComp -$Comp -L Device:C_Small C9 -U 1 1 5FEF828C -P 5100 1100 -F 0 "C9" H 5008 1054 50 0000 R CNN -F 1 "0.1uF" H 5008 1145 50 0000 R CNN -F 2 "" H 5100 1100 50 0001 C CNN -F 3 "~" H 5100 1100 50 0001 C CNN - 1 5100 1100 - -1 0 0 1 -$EndComp -$Comp -L Device:R R7 -U 1 1 5FF0FBDF -P 4850 1300 -F 0 "R7" V 4750 1250 50 0000 L CNN -F 1 "120R" V 4850 1200 50 0000 L CNN -F 2 "" V 4780 1300 50 0001 C CNN -F 3 "~" H 4850 1300 50 0001 C CNN - 1 4850 1300 - 0 1 1 0 -$EndComp -$Comp -L power:VCC #PWR018 -U 1 1 5FF26567 -P 5100 1000 -F 0 "#PWR018" H 5100 850 50 0001 C CNN -F 1 "VCC" H 5117 1173 50 0000 C CNN -F 2 "" H 5100 1000 50 0001 C CNN -F 3 "" H 5100 1000 50 0001 C CNN - 1 5100 1000 - 1 0 0 -1 -$EndComp -$Comp -L 74xx:74HC14 U1 -U 4 1 5FF485F0 -P 6200 1300 -F 0 "U1" H 6150 1450 50 0000 L CNN -F 1 "74HC14" H 6150 1150 50 0000 L CNN -F 2 "" H 6200 1300 50 0001 C CNN -F 3 "http://www.ti.com/lit/gpn/sn74HC14" H 6200 1300 50 0001 C CNN - 4 6200 1300 - 1 0 0 -1 -$EndComp -Wire Wire Line - 6500 1300 6800 1300 -Wire Wire Line - 5000 1300 5100 1300 -Wire Wire Line - 5100 1200 5100 1300 -Wire Bus Line - 6350 2600 6350 3200 -Wire Bus Line - 3000 1100 3000 2600 -Wire Bus Line - 6400 3400 6400 4400 -Wire Bus Line - 4550 3600 4550 5850 -Wire Bus Line - 3000 4650 3000 5850 -Wire Bus Line - 3150 2600 3150 4800 -Wire Bus Line - 4700 2600 4700 4600 -Wire Bus Line - 3000 2600 3000 4250 -Connection ~ 5100 1300 -Wire Wire Line - 5100 1300 5300 1300 -Text Notes 5350 950 0 50 ~ 0 -Delay the UART ~CS~ for a few ns to bring the\ntiming between R/~W~ and ~CS~ within spec\n(this might have been a red herring and not necessary) -$EndSCHEMATC