4 #define DMA_ENABLE 0x80000000
5 #define DMA_INT_ENABLE 0x40000000
6 #define DMA_TIMING_IMMED 0x00000000
7 #define DMA_TIMING_VBLANK 0x10000000
8 #define DMA_TIMING_HBLANK 0x20000000
9 #define DMA_TIMING_DISPSYNC 0x30000000
10 #define DMA_16 0x00000000
11 #define DMA_32 0x04000000
12 #define DMA_REPEAT 0x02000000
13 #define DMA_SRC_INC 0x00000000
14 #define DMA_SRC_DEC 0x00800000
15 #define DMA_SRC_FIX 0x01000000
16 #define DMA_DST_INC 0x00000000
17 #define DMA_DST_DEC 0x00200000
18 #define DMA_DST_FIX1 0x00400000
19 #define DMA_DST_RELOAD 0x00600000
21 /* DMA Register Parts */
26 static volatile uint32_t *reg_dma[4] = {(void*)0x040000b0, (void*)0x040000bc, (void*)0x040000c8, (void*)0x040000d4 };
28 /* --- perform a copy of words or halfwords using DMA --- */
30 void dma_copy32(int channel, void *dst, void *src, int words, unsigned int flags)
32 reg_dma[channel][DMA_SRC] = (uint32_t)src;
33 reg_dma[channel][DMA_DST] = (uint32_t)dst;
34 reg_dma[channel][DMA_CTRL] = words | flags | DMA_32 | DMA_ENABLE;
37 void dma_copy16(int channel, void *dst, void *src, int halfwords, unsigned int flags)
39 reg_dma[channel][DMA_SRC] = (uint32_t)src;
40 reg_dma[channel][DMA_DST] = (uint32_t)dst;
41 reg_dma[channel][DMA_CTRL] = halfwords | flags | DMA_16 | DMA_ENABLE;
44 /* --- fill a buffer with an ammount of words and halfwords using DMA --- */
46 static uint32_t fill[4];
48 void dma_fill32(int channel, void *dst, uint32_t val, int words)
51 reg_dma[channel][DMA_SRC] = (uint32_t)(fill + channel);
52 reg_dma[channel][DMA_DST] = (uint32_t)dst;
53 reg_dma[channel][DMA_CTRL] = words | DMA_SRC_FIX | DMA_TIMING_IMMED | DMA_32 | DMA_ENABLE;
56 void dma_fill16(int channel, void *dst, uint16_t val, int halfwords)
59 reg_dma[channel][DMA_SRC] = (uint32_t)(fill + channel);
60 reg_dma[channel][DMA_DST] = (uint32_t)dst;
61 reg_dma[channel][DMA_CTRL] = halfwords | DMA_SRC_FIX | DMA_TIMING_IMMED | DMA_16 | DMA_ENABLE;