6 #define UART0_BASE (IO_BASE | 0x201000)
7 #define UART0_REG(x) (*(volatile uint32_t*)(UART0_BASE | (x)))
9 #define REG_DR UART0_REG(0x00) /* data register */
10 #define REG_RSRECR UART0_REG(0x04) /* receive status & error clear */
11 #define REG_FR UART0_REG(0x18) /* flag register */
12 #define REG_IBRD UART0_REG(0x24) /* integer baud rate divisor (low 16 bits) */
13 #define REG_FBRD UART0_REG(0x28) /* fractional baud rate divisor (low 6 (six) bits) */
14 #define REG_LCRH UART0_REG(0x2c) /* line control */
15 #define REG_CR UART0_REG(0x30) /* control register */
16 #define REG_IFLS UART0_REG(0x34) /* interrupt FIFO level select */
17 #define REG_IMSC UART0_REG(0x38) /* interrupt mask set clear */
18 #define REG_RIS UART0_REG(0x3c) /* raw interrupt status */
19 #define REG_MIS UART0_REG(0x40) /* masked interrupt status */
20 #define REG_ICR UART0_REG(0x44) /* interrupt clear */
22 /* error bits in REG_DR */
28 /* receive status error bits */
34 /* flag register bits */
37 #define FR_RXFE 0x10 /* receive FIFO empty */
38 #define FR_TXFF 0x20 /* transmit FIFO full */
39 #define FR_RXFF 0x40 /* receive FIFO full */
40 #define FR_TXFE 0x80 /* transmit FIFO empty */
42 /* line control register bits */
43 #define LCRH_BRK 0x01 /* send break */
44 #define LCRH_PAREN 0x02
45 #define LCRH_PAREVEN 0x04
46 #define LCRH_STOP2 0x08
47 #define LCRH_FIFOEN 0x10
48 #define LCRH_8BITS 0x60
49 #define LCRH_7BITS 0x40
50 #define LCRH_STICKPAR 0x80 /* ? */
52 /* control register bits */
53 #define CR_UARTEN 0x0001
54 #define CR_LOOPEN 0x0080
55 #define CR_TXEN 0x0100
56 #define CR_RXEN 0x0200
58 #define CR_RTSEN 0x4000
59 #define CR_CTSEN 0x8000
61 /* interrupt bits for IMSC, RIS, ICR */
65 #define I_RTIME 0x0040
71 #endif /* UART_PL011_H_ */