/* ---- DMA registers ---- */
#define REG_DMA0SAD REG32(0xb0)
#define REG_DMA0DAD REG32(0xb4)
+#define REG_DMA0CNT REG32(0xb8)
#define REG_DMA0CNT_L REG16(0xb8)
#define REG_DMA0CNT_H REG16(0xba)
#define REG_DMA1SAD REG32(0xbc)
#define REG_DMA1DAD REG32(0xc0)
+#define REG_DMA1CNT REG32(0xc4)
#define REG_DMA1CNT_L REG16(0xc4)
#define REG_DMA1CNT_H REG16(0xc6)
#define REG_DMA2SAD REG32(0xc8)
#define REG_DMA2DAD REG32(0xcc)
+#define REG_DMA2CNT REG32(0xd0)
#define REG_DMA2CNT_L REG16(0xd0)
#define REG_DMA2CNT_H REG16(0xd2)
#define REG_DMA3SAD REG32(0xd4)
#define REG_DMA3DAD REG32(0xd8)
+#define REG_DMA3CNT REG32(0xdc)
#define REG_DMA3CNT_L REG16(0xdc)
#define REG_DMA3CNT_H REG16(0xde)
#define DMACNT_IEN 0x40000000
#define DMACNT_EN 0x80000000
+/* REG_WAITCNT bits */
+#define WAITCNT_ROM_4_2 0x0000
+#define WAITCNT_ROM_3_2 0x0004
+#define WAITCNT_ROM_2_2 0x0008
+#define WAITCNT_ROM_8_2 0x000c
+#define WAITCNT_ROM_4_1 0x0010
+#define WAITCNT_ROM_3_1 0x0014
+#define WAITCNT_ROM_2_1 0x0018
+#define WAITCNT_ROM_8_1 0x001c
+#define WAITCNT_PREFETCH 0x4000
#endif /* GBAREGS_H_ */