.section .startup
.code 32
+ .global startup
startup:
- ldr sp, =_stacktop
-
- mov r0, #2
- bl dbgled
+ cpsid if
+
+ @ stop all but one of the cores
+ mrc p15, 0, r0, c0, c0, 5
+ ands r0, r0, #0xff
+ bne exit
+
+ @ detect if we're running in hyp mode, and drop to svc
+ mrs r0, cpsr
+ and r1, r0, #0x1f
+ cmp r1, #0x1a
+ bne hypend
+
+ bic r0, #0x1f
+ orr r0, #0x13
+ @msr spsr_cxsf, r0
+ add r0, pc, #4
+ msr elr_hyp, r0
+ @eret
+ mov pc, r0
+hypend:
+
+ @ setup initial stacks, allow 4k stack for IRQs
+ @mov r0, #0x12 @ switch to IRQ mode
+ @msr cpsr, r0
+ @ldr sp, =_stacktop
+ @mov r0, #0x13 @ switch to supervisor mode
+ @msr cpsr, r0
+ ldr sp, =_stacktop - 4096
@ clear bss
ldr r0, =_bss_start
subs r1, #4
bne 0b
1:
- bl main
-
- mov r0, #0
- bl dbgled
+ blx main
.global exit
exit: wfe
b exit
- .global dbgled
-dbgled:
- ldr r3, =0x3f200000 @ gpio base
- ldr r2, =0x9000 @ gpio 24 and 25 -> output
- str r2, [r3, #8] @ store to GPFSEL2
- ldr r2, =0x01000000 @ bit 24
- tst r0, #1
- strne r2, [r3, #0x1c] @ GPSET0
- streq r2, [r3, #0x28] @ GPCLR0
- lsl r2, #1
- tst r0, #2
- strne r2, [r3, #0x1c] @ GPSET0
- streq r2, [r3, #0x28] @ GPCLR0
- bx lr
-
- .global delay
-delay:
- subs r0, r0, #1
- bne delay
- bx lr
-
@ vi:set filetype=armasm: