5 .set read_retries, 0x7be8
6 .set drive_number, 0x7bec
8 .set scratchbuf, 0x7bf0
9 .set scratchbuf_size, 16
13 # move stack to just below the code
17 # use the code segment for data access
31 # load the second stage boot loader and jump to it
32 mov $_boot2_size, %eax
42 # set es to the start of the destination buffer to allow reading in
54 loading_msg: .asciz "\nLoad "
55 driveno_msg: .asciz "Drive: "
57 sect_per_track: .short 18
58 num_cylinders: .short 80
66 movb drive_number, %dl
83 mov %ax, num_cylinders
86 mov %cx, sect_per_track
104 # read_sectors(first, num)
109 mov ARG_SIDX(%bp), %ax
118 1: cmp ARG_NSECT(%bp), %cx
131 movw $3, read_retries
134 # calculate the track (sidx / sectors_per_track)
138 mov sect_per_track, %cx
146 # cylinder (track/heads) in ch [0-7] and cl[6,7]<-[8,9]
156 # sector num cl[0-5] is sidx % sectors_per_track + 1
161 # ah = 2 (read), al = 1 sectors
163 movb drive_number, %dl
167 # abort after 3 attempts
171 # error detected, reset controller and retry
184 # increment es:bx accordingly (advance es if bx overflows)
196 str_read_error: .asciz "rderr: "
199 mov $str_read_error, %si
207 # expects string pointer in ds:si
221 # expects character in al
237 # expects number in eax
243 movw $scratchbuf + scratchbuf_size, %si
261 .set UART_DATA, 0x3f8
262 .set UART_DIVLO, 0x3f8
263 .set UART_DIVHI, 0x3f9
264 .set UART_FIFO, 0x3fa
265 .set UART_LCTL, 0x3fb
266 .set UART_MCTL, 0x3fc
267 .set UART_LSTAT, 0x3fd
268 .set DIV_9600, 115200 / 9600
271 .set FIFO_ENABLE, 0x01
272 .set FIFO_SEND_CLEAR, 0x04
273 .set FIFO_RECV_CLEAR, 0x02
277 .set LST_TREG_EMPTY, 0x20
294 # clear and enable fifo
295 mov $FIFO_ENABLE, %al
296 or $FIFO_SEND_CLEAR, %al
297 or $FIFO_RECV_CLEAR, %al
308 # expects a character in al
321 # wait until the transmit register is empty
324 and $LST_TREG_EMPTY, %al