9efade4292168e8fabe550557b4944f96085da15
[gbajam21] / src / dma.c
1 #include "dma.h"
2
3 /* DMA Options */
4 #define DMA_ENABLE                              0x80000000
5 #define DMA_INT_ENABLE                  0x40000000
6 #define DMA_TIMING_IMMED                0x00000000
7 #define DMA_TIMING_VBLANK               0x10000000
8 #define DMA_TIMING_HBLANK               0x20000000
9 #define DMA_TIMING_DISPSYNC             0x30000000
10 #define DMA_16                                  0x00000000
11 #define DMA_32                                  0x04000000
12 #define DMA_REPEAT                              0x02000000
13 #define DMA_SRC_INC                             0x00000000
14 #define DMA_SRC_DEC                             0x00800000
15 #define DMA_SRC_FIX                             0x01000000
16 #define DMA_DST_INC                             0x00000000
17 #define DMA_DST_DEC                             0x00200000
18 #define DMA_DST_FIX1                    0x00400000
19 #define DMA_DST_RELOAD                  0x00600000
20
21 /* DMA Register Parts */
22 #define DMA_SRC         0
23 #define DMA_DST         1
24 #define DMA_CTRL        2
25
26 static volatile uint32_t *reg_dma[4] = {(void*)0x040000b0, (void*)0x040000bc, (void*)0x040000c8, (void*)0x040000d4 };
27
28 void AAS_DoDMA3(void*, void*, uint32_t);
29
30 /* --- perform a copy of words or halfwords using DMA --- */
31
32 void dma_copy32(int channel, void *dst, void *src, int words, unsigned int flags)
33 {
34         if(channel == 3) {
35                 AAS_DoDMA3(src, dst, words | flags | DMA_32 | DMA_ENABLE);
36         } else {
37                 reg_dma[channel][DMA_SRC] = (uint32_t)src;
38                 reg_dma[channel][DMA_DST] = (uint32_t)dst;
39                 reg_dma[channel][DMA_CTRL] = words | flags | DMA_32 | DMA_ENABLE;
40         }
41 }
42
43 void dma_copy16(int channel, void *dst, void *src, int halfwords, unsigned int flags)
44 {
45         if(channel == 3) {
46                 AAS_DoDMA3(src, dst, halfwords | flags | DMA_16 | DMA_ENABLE);
47         } else {
48                 reg_dma[channel][DMA_SRC] = (uint32_t)src;
49                 reg_dma[channel][DMA_DST] = (uint32_t)dst;
50                 reg_dma[channel][DMA_CTRL] = halfwords | flags | DMA_16 | DMA_ENABLE;
51         }
52 }
53
54 /* --- fill a buffer with an ammount of words and halfwords using DMA --- */
55
56 static uint32_t fill[4];
57
58 void dma_fill32(int channel, void *dst, uint32_t val, int words)
59 {
60         fill[channel] = val;
61         if(channel == 3) {
62                 AAS_DoDMA3(fill + channel, dst, words | DMA_SRC_FIX | DMA_TIMING_IMMED | DMA_32 | DMA_ENABLE);
63         } else {
64                 reg_dma[channel][DMA_SRC] = (uint32_t)(fill + channel);
65                 reg_dma[channel][DMA_DST] = (uint32_t)dst;
66                 reg_dma[channel][DMA_CTRL] = words | DMA_SRC_FIX | DMA_TIMING_IMMED | DMA_32 | DMA_ENABLE;
67         }
68 }
69
70 void dma_fill16(int channel, void *dst, uint16_t val, int halfwords)
71 {
72         fill[channel] = val;
73         if(channel == 3) {
74                 AAS_DoDMA3(fill + channel, dst, halfwords | DMA_SRC_FIX | DMA_TIMING_IMMED | DMA_16 | DMA_ENABLE);
75         } else {
76                 reg_dma[channel][DMA_SRC] = (uint32_t)(fill + channel);
77                 reg_dma[channel][DMA_DST] = (uint32_t)dst;
78                 reg_dma[channel][DMA_CTRL] = halfwords | DMA_SRC_FIX | DMA_TIMING_IMMED | DMA_16 | DMA_ENABLE;
79         }
80 }