6 #define VRAM_START_ADDR 0x6000000
7 #define VRAM_BG_ADDR VRAM_START_ADDR
8 #define VRAM_OBJ_ADDR 0x6010000
9 #define VRAM_LFB_OBJ_ADDR 0x6014000
10 #define VRAM_LFB_FB0_ADDR VRAM_START_ADDR
11 #define VRAM_LFB_FB1_ADDR 0x600a000
13 /* address of character data block x (4 possible blocks, 16k each) */
14 #define VRAM_CHR_BLOCK_ADDR(x) (VRAM_START_ADDR + ((x) << 14))
15 /* address of screen data block x (32 possible blocks, 2k each) */
16 #define VRAM_SCR_BLOCK_ADDR(x) (VRAM_START_ADDR + ((x) << 11))
18 /* fields of a background tile in screen memory */
19 #define BGTILE_HFLIP 0x0400
20 #define BGTILE_VFLIP 0x0800
21 #define BGTILE_PAL(x) ((uint16_t)(x) << 12)
23 /* color palette ram addresses for backgrounds and sprites */
24 #define CRAM_BG_ADDR 0x5000000
25 #define CRAM_OBJ_ADDR 0x5000200
28 #define OAM_ADDR 0x7000000
30 /* interrupt handler */
31 #define INTR_VECTOR (*(volatile uint32_t*)0x3007ffc)
33 /* battery backed RAM address */
34 #define SRAM_ADDR 0xe000000
38 #define REG_BASE 0x4000000
39 #define REG8(x) (*(volatile uint8_t*)(REG_BASE + (x)))
40 #define REG16(x) (*(volatile uint16_t*)(REG_BASE + (x)))
41 #define REG32(x) (*(volatile uint32_t*)(REG_BASE + (x)))
43 /* ---- display registers ---- */
44 #define REG_DISPCNT REG16(0x00)
45 #define REG_GREENSWAP REG16(0x02)
46 #define REG_DISPSTAT REG16(0x04)
47 #define REG_VCOUNT REG16(0x06)
48 #define REG_BG0CNT REG16(0x08)
49 #define REG_BG1CNT REG16(0x0a)
50 #define REG_BG2CNT REG16(0x0c)
51 #define REG_BG3CNT REG16(0x0e)
52 /* scrolling registers */
53 #define REG_BG0HOFS REG16(0x10)
54 #define REG_BG0VOFS REG16(0x12)
55 #define REG_BG1HOFS REG16(0x14)
56 #define REG_BG1VOFS REG16(0x16)
57 #define REG_BG2HOFS REG16(0x18)
58 #define REG_BG2VOFS REG16(0x1a)
59 #define REG_BG3HOFS REG16(0x1c)
60 #define REG_BG3VOFS REG16(0x1e)
61 /* BG rotation and scaling registers */
62 #define REG_BG2PA REG16(0x20)
63 #define REG_BG2PB REG16(0x22)
64 #define REG_BG2PC REG16(0x24)
65 #define REG_BG2PD REG16(0x26)
66 #define REG_BG2X REG32(0x28)
67 #define REG_BG2Y REG32(0x2c)
68 #define REG_BG3PA REG16(0x30)
69 #define REG_BG3PB REG16(0x32)
70 #define REG_BG3PC REG16(0x34)
71 #define REG_BG3PD REG16(0x36)
72 #define REG_BG3X REG32(0x38)
73 #define REG_BG3Y REG32(0x3c)
74 /* window registers */
75 #define REG_WIN0H REG16(0x40)
76 #define REG_WIN1H REG16(0x42)
77 #define REG_WIN0V REG16(0x44)
78 #define REG_WIN1V REG16(0x46)
79 #define REG_WININ REG16(0x48)
80 #define REG_WINOUT REG16(0x4a)
82 #define REG_MOSAIC REG16(0x4c)
84 #define REG_BLDCNT REG16(0x50)
85 #define REG_BLDALPHA REG16(0x52)
86 #define REG_BLDY REG16(0x54)
88 /* ---- sound registers ---- */
89 #define REG_SOUND1CNT_L REG16(0x60)
90 #define REG_SOUND1CNT_H REG16(0x62)
91 #define REG_SOUND1CNT_X REG16(0x64)
92 #define REG_SOUND2CNT_L REG16(0x68)
93 #define REG_SOUND2CNT_H REG16(0x6c)
94 #define REG_SOUND3CNT_L REG16(0x70)
95 #define REG_SOUND3CNT_H REG16(0x72)
96 #define REG_SOUND3CNT_X REG16(0x74)
97 #define REG_SOUND4CNT_L REG16(0x78)
98 #define REG_SOUND4CNT_H REG16(0x7c)
99 #define REG_SOUNDCNT_L REG16(0x80)
100 #define REG_SOUNDCNT_H REG16(0x82)
101 #define REG_SOUNDCNT_X REG16(0x84)
102 #define REG_SOUNDBIAS REG16(0x88)
103 #define WAVE_RAM_PTR ((unsigned char*)(REG_BASE + 0x90))
104 #define REG_FIFO_A REG32(0xa0)
105 #define REG_FIFO_B REG32(0xa4)
106 #define FIFO_A_PTR ((unsigned char*)(REG_BASE + 0xa0))
107 #define FIFO_B_PTR ((unsigned char*)(REG_BASE + 0xa4))
109 /* ---- DMA registers ---- */
110 #define REG_DMA0SAD REG32(0xb0)
111 #define REG_DMA0DAD REG32(0xb4)
112 #define REG_DMA0CNT REG32(0xb8)
113 #define REG_DMA0CNT_L REG16(0xb8)
114 #define REG_DMA0CNT_H REG16(0xba)
115 #define REG_DMA1SAD REG32(0xbc)
116 #define REG_DMA1DAD REG32(0xc0)
117 #define REG_DMA1CNT REG32(0xc4)
118 #define REG_DMA1CNT_L REG16(0xc4)
119 #define REG_DMA1CNT_H REG16(0xc6)
120 #define REG_DMA2SAD REG32(0xc8)
121 #define REG_DMA2DAD REG32(0xcc)
122 #define REG_DMA2CNT REG32(0xd0)
123 #define REG_DMA2CNT_L REG16(0xd0)
124 #define REG_DMA2CNT_H REG16(0xd2)
125 #define REG_DMA3SAD REG32(0xd4)
126 #define REG_DMA3DAD REG32(0xd8)
127 #define REG_DMA3CNT REG32(0xdc)
128 #define REG_DMA3CNT_L REG16(0xdc)
129 #define REG_DMA3CNT_H REG16(0xde)
131 /* ---- timer registers ---- */
132 #define REG_TM0CNT_L REG16(0x100)
133 #define REG_TM0CNT_H REG16(0x102)
134 #define REG_TM1CNT_L REG16(0x104)
135 #define REG_TM1CNT_H REG16(0x106)
136 #define REG_TM2CNT_L REG16(0x108)
137 #define REG_TM2CNT_H REG16(0x10a)
138 #define REG_TM3CNT_L REG16(0x10c)
139 #define REG_TM3CNT_H REG16(0x10e)
141 #define REG_TMCNT_L(x) REG16(0x100 + ((x) << 2))
142 #define REG_TMCNT_H(x) REG16(0x102 + ((x) << 2))
144 /* ---- communication registers (serial/joybus/gpio) ---- */
145 #define REG_SIODATA32 REG32(0x120)
146 #define REG_SIOMULTI0 REG16(0x120)
147 #define REG_SIOMULTI1 REG16(0x122)
148 #define REG_SIOMULTI2 REG16(0x124)
149 #define REG_SIOMULTI3 REG16(0x126)
150 #define REG_SIOCNT REG16(0x128)
151 #define REG_SIOMLT_SEND REG16(0x12a)
152 #define REG_SIODATA8 REG16(0x12a)
153 #define REG_RCNT REG16(0x134)
154 #define REG_JOYCNT REG16(0x140)
155 #define REG_JOY_RECV REG32(0x150)
156 #define REG_JOY_TRANS REG32(0x154)
157 #define REG_JOYSTAT REG16(0x158)
159 /* ---- keypad registers ---- */
160 #define REG_KEYINPUT REG16(0x130)
161 #define REG_KEYCNT REG16(0x132)
163 /* ---- interrupts ---- */
164 #define REG_IE REG16(0x200)
165 #define REG_IF REG16(0x202)
166 #define REG_WAITCNT REG16(0x204)
167 #define REG_IME REG16(0x208)
169 #define REG_POSTFLG REG8(0x300)
170 #define REG_HALTCNT REG8(0x301)
171 #define REG_INTMEMCNT REG32(0x800)
173 /* REG_DISPSTAT bits */
174 #define DISPSTAT_VBLANK 0x01
175 #define DISPSTAT_HBLANK 0x02
176 #define DISPSTAT_VMATCH 0x04
177 #define DISPSTAT_IEN_VBLANK 0x08
178 #define DISPSTAT_IEN_HBLANK 0x10
179 #define DISPSTAT_IEN_VMATCH 0x20
180 #define DISPSTAT_VCOUNT(x) ((uint16_t)(x) << 8)
182 /* REG_DISPCNT bits */
183 #define DISPCNT_MODE(x) (x)
184 #define DISPCNT_FB1 0x0010
185 #define DISPCNT_HBLANK_OBJPROC 0x0020
186 #define DISPCNT_OBJMAP_1D 0x0040
187 #define DISPCNT_FORCE_BLANK 0x0080
188 #define DISPCNT_BG0 0x0100
189 #define DISPCNT_BG1 0x0200
190 #define DISPCNT_BG2 0x0400
191 #define DISPCNT_BG3 0x0800
192 #define DISPCNT_OBJ 0x1000
193 #define DISPCNT_WIN0 0x2000
194 #define DISPCNT_WIN1 0x4000
195 #define DISPCNT_WINOBJ 0x8000
197 /* REG_BGXCNT bits */
198 #define BGCNT_PRIO(x) ((uint16_t)(x))
199 #define BGCNT_CHR_BASE(x) ((uint16_t)(x) << 2)
200 #define BGCNT_MOSAIC 0x0040
201 #define BGCNT_256COL 0x0080
202 #define BGCNT_SCR_BASE(x) ((uint16_t)(x) << 8)
203 #define BGCNT_WRAP 0x2000
205 #define BGCNT_SZ(x) ((uint16_t)(x) << 14)
206 #define BGCNT_SZ_TX_256X256 BGCNT_SZ(0)
207 #define BGCNT_SZ_RS_128X128 BGCNT_SZ(0)
208 #define BGCNT_SZ_TX_512X256 BGCNT_SZ(1)
209 #define BGCNT_SZ_RS_256X256 BGCNT_SZ(1)
210 #define BGCNT_SZ_TX_256X512 BGCNT_SZ(2)
211 #define BGCNT_SZ_RS_512X512 BGCNT_SZ(2)
212 #define BGCNT_SZ_TX_512X512 BGCNT_SZ(3)
213 #define BGCNT_SZ_RS_1024X1024 BGCNT_SZ(3)
215 /* REG_BLDCNT bits */
216 #define BLDCNT_A_BG0 0x0001
217 #define BLDCNT_A_BG1 0x0002
218 #define BLDCNT_A_BG2 0x0004
219 #define BLDCNT_A_BG3 0x0008
220 #define BLDCNT_A_OBJ 0x0010
221 #define BLDCNT_A_BACKDROP 0x0020
222 #define BLDCNT_B_BG0 0x0100
223 #define BLDCNT_B_BG1 0x0200
224 #define BLDCNT_B_BG2 0x0400
225 #define BLDCNT_B_BG3 0x0800
226 #define BLDCNT_B_OBJ 0x1000
227 #define BLDCNT_B_BACKDROP 0x2000
229 #define BLDCNT_ALPHA 0x0040
230 #define BLDCNT_BRIGHTEN 0x0080
231 #define BLDCNT_DARKEN 0x00c0
234 #define IF_VBLANK 0x0001
235 #define IF_HBLANK 0x0002
236 #define IF_VMATCH 0x0004
237 #define IF_TIMER0 0x0008
238 #define IF_TIMER1 0x0010
239 #define IF_TIMER2 0x0020
240 #define IF_TIMER3 0x0040
241 #define IF_COMM 0x0080
242 #define IF_DMA0 0x0100
243 #define IF_DMA1 0x0200
244 #define IF_DMA2 0x0400
245 #define IF_DMA3 0x0800
246 #define IF_KEY 0x1000
247 #define IF_GPAK 0x2000
249 /* REG_TMXCNT bits */
250 #define TMCNT_PRESCL_CLK1 0
251 #define TMCNT_PRESCL_CLK64 1
252 #define TMCNT_PRESCL_CLK256 2
253 #define TMCNT_PRESCL_CLK1024 3
255 #define TMCNT_CASCADE 0x04
256 #define TMCNT_IE 0x40
257 #define TMCNT_EN 0x80
262 #define KEY_SELECT 0x0004
263 #define KEY_START 0x0008
264 #define KEY_RIGHT 0x0010
265 #define KEY_LEFT 0x0020
266 #define KEY_UP 0x0040
267 #define KEY_DOWN 0x0080
268 #define KEY_RT 0x0100
269 #define KEY_LT 0x0200
271 #define KEYCNT_IE 0x4000
272 #define KEYCNT_IAND 0x8000
274 /* REG_SOUNDCNT_L bits */
275 #define SCNT_SS_LVOL(x) ((x) & 7)
276 #define SCNT_SS_RVOL(x) (((x) & 7) << 4)
277 #define SCNT_SS_VOL(x) (SCNT_SS_LVOL(x) | SCNT_SS_RVOL(x))
278 #define SCNT_SS1_EN_R 0x0100
279 #define SCNT_SS2_EN_R 0x0200
280 #define SCNT_SS3_EN_R 0x0400
281 #define SCNT_SS4_EN_R 0x0800
282 #define SCNT_SS_EN_R(x) (SCNT_SS1_EN_R << (x))
283 #define SCNT_SS1_EN_L 0x1000
284 #define SCNT_SS2_EN_L 0x2000
285 #define SCNT_SS3_EN_L 0x4000
286 #define SCNT_SS4_EN_L 0x8000
287 #define SCNT_SS_EN_L(x) (SCNT_SS1_EN_L << (x))
288 #define SCNT_SS1_EN (SCNT_SS1_EN_R | SCNT_SS1_EN_L)
289 #define SCNT_SS2_EN (SCNT_SS2_EN_R | SCNT_SS2_EN_L)
290 #define SCNT_SS3_EN (SCNT_SS3_EN_R | SCNT_SS3_EN_L)
291 #define SCNT_SS4_EN (SCNT_SS4_EN_R | SCNT_SS4_EN_L)
292 #define SCNT_SS_EN(x) (SCNT_SS_EN_L(x) | SCNT_SS_EN_R(x))
299 /* REG_SOUNDCNT_X bits */
300 #define SCNT_MASTER_EN 0x0080
302 /* REG_SOUNDCNT_H bits */
303 #define SCNT_SS_VOL_QRT 0x0000
304 #define SCNT_SS_VOL_HALF 0x0001
305 #define SCNT_SS_VOL_FULL 0x0002
306 #define SCNT_DSA_VOL_HALF 0
307 #define SCNT_DSA_VOL_FULL 0x0004
308 #define SCNT_DSB_VOL_HALF 0
309 #define SCNT_DSB_VOL_FULL 0x0008
310 #define SCNT_DSA_EN_R 0x0100
311 #define SCNT_DSA_EN_L 0x0200
312 #define SCNT_DSA_TIMER0 0
313 #define SCNT_DSA_TIMER1 0x0400
314 #define SCNT_DSA_CLRFIFO 0x0800
315 #define SCNT_DSB_EN_R 0x1000
316 #define SCNT_DSB_EN_L 0x2000
317 #define SCNT_DSB_TIMER0 0
318 #define SCNT_DSB_TIMER1 0x4000
319 #define SCNT_DSB_CLRFIFO 0x8000
321 /* REG_DMAxCNT_H bits */
322 #define DMACNTH_DST_INC 0
323 #define DMACNTH_DST_DEC 0x0020
324 #define DMACNTH_DST_FIXED 0x0040
325 #define DMACNTH_INC_RELOAD 0x0060
326 #define DMACNTH_SRC_INC 0
327 #define DMACNTH_SRC_DEC 0x0080
328 #define DMACNTH_SRC_FIXED 0x0100
329 #define DMACNTH_REPEAT 0x0200
330 #define DMACNTH_16BIT 0
331 #define DMACNTH_32BIT 0x0400
332 #define DMACNTH_VBLANK 0x1000
333 #define DMACNTH_HBLANK 0x2000
334 #define DMACNTH_SOUND 0x3000
335 #define DMACNTH_IEN 0x4000
336 #define DMACNTH_EN 0x8000
338 #define DMACNT_DST_INC 0
339 #define DMACNT_DST_DEC 0x00200000
340 #define DMACNT_DST_FIXED 0x00400000
341 #define DMACNT_INC_RELOAD 0x00600000
342 #define DMACNT_SRC_INC 0
343 #define DMACNT_SRC_DEC 0x00800000
344 #define DMACNT_SRC_FIXED 0x01000000
345 #define DMACNT_REPEAT 0x02000000
346 #define DMACNT_16BIT 0
347 #define DMACNT_32BIT 0x04000000
348 #define DMACNT_VBLANK 0x10000000
349 #define DMACNT_HBLANK 0x20000000
350 #define DMACNT_SPECIAL 0x30000000
351 #define DMACNT_SOUND DMACNT_SPECIAL
352 #define DMACNT_VIDEO DMACNT_SPECIAL
353 #define DMACNT_IEN 0x40000000
354 #define DMACNT_EN 0x80000000
356 /* REG_WAITCNT bits */
357 #define WAITCNT_ROM_4_2 0x0000
358 #define WAITCNT_ROM_3_2 0x0004
359 #define WAITCNT_ROM_2_2 0x0008
360 #define WAITCNT_ROM_8_2 0x000c
361 #define WAITCNT_ROM_4_1 0x0010
362 #define WAITCNT_ROM_3_1 0x0014
363 #define WAITCNT_ROM_2_1 0x0018
364 #define WAITCNT_ROM_8_1 0x001c
365 #define WAITCNT_PREFETCH 0x4000
367 #endif /* GBAREGS_H_ */
projects / gbajam22 / blob