6 Accessing different peripherals migh return results out of order. See bcm2835
7 spec section 1.3. Use memory barriers as follows:
8 - place write barrier before the first write to a peripheral
9 - place read barrier after the last read of a peripheral
11 Multiple accesses to the same peripheral in a row do not require barriers.
13 Interrupt handlers should have a read barrier before their first read, and end
18 Two types of cache management:
19 - cache cleaning (write-back caches)
20 - cache invalidation (all caches)
22 Cache clean and invalidate operations are also needed before the GPU can see our
23 command buffers... see:
24 https://github.com/rsta2/uspi/blob/38eaff4f715643a9/lib/synchronize.c
28 RAM is mapped to 0, 40000000 (cache-coherent) and c0000000h (uncached) in VC
29 space. In the ARM address space is mapped to 0(?).
31 I/O base is at 7e000000 in VC address space (rpi1?), and mapped to different
32 ranges for each model in ARM space.