10 void intr_entry_nop();
11 void intr_entry_irq();
15 /* setup interrupt vectors */
16 setvect(INTR_RESET, (uint32_t)startup);
17 setvect(INTR_UNDEF, (uint32_t)intr_entry_nop);
18 setvect(INTR_SWI, (uint32_t)intr_entry_nop);
19 setvect(INTR_IABORT, (uint32_t)intr_entry_nop);
20 setvect(INTR_DABORT, (uint32_t)intr_entry_nop);
21 setvect(INTR_IRQ, (uint32_t)intr_entry_irq);
22 setvect(INTR_FIQ, (uint32_t)intr_entry_irq);
24 printf("Exception vectors:\n");
28 void setvect(int idx, uint32_t addr)
31 uint32_t pc = (idx << 2) + 8;
33 printf("setvect(%d, %lx)\n", idx, (unsigned long)addr);
35 /* construct branch instruction */
36 ivec[idx] = 0xea000000 | (addr - pc) >> 2;
38 /* we also probably need to invalidate the instr. cache */
39 sysctl_icache_inval(0, 32);
42 void enable_arm_irq(int irq)
45 if(irq == IRQ_TIMER) {
46 IRQ_FIQCTL_REG = IRQ_FIQCTL_SELARM(IRQ_TIMER) | IRQ_FIQCTL_ENABLE;
48 IRQ_ENABLE0_REG |= 1 << irq;
53 void disable_arm_irq(int irq)
56 if(irq == IRQ_TIMER) {
59 IRQ_ENABLE0_REG &= ~(1 << irq);
64 void enable_gpu_irq(int irq)
67 /*if(irq == IRQ_GPU_TIMER1) {
68 IRQ_FIQCTL_REG = IRQ_FIQCTL_SELGPU(IRQ_GPU_TIMER1) | IRQ_FIQCTL_ENABLE;
69 } else */if(irq < 32) {
70 IRQ_ENABLE1_REG |= 1 << irq;
72 IRQ_ENABLE2_REG |= 1 << (irq - 32);
77 void disable_gpu_irq(int irq)
80 /*if(irq == IRQ_GPU_TIMER1) {
82 } else */if(irq < 32) {
83 IRQ_ENABLE1_REG &= ~(1 << irq);
85 IRQ_ENABLE2_REG &= ~(1 << (irq - 32));