5 void enable_arm_irq(int irq)
9 IRQ_FIQCTL_REG = IRQ_FIQCTL_SELARM(IRQ_TIMER) | IRQ_FIQCTL_ENABLE;
11 IRQ_ENABLE0_REG |= 1 << irq;
16 void disable_arm_irq(int irq)
19 if(irq == IRQ_TIMER) {
22 IRQ_ENABLE0_REG &= ~(1 << irq);
27 void enable_gpu_irq(int irq)
30 if(irq == IRQ_GPU_TIMER1) {
31 IRQ_FIQCTL_REG = IRQ_FIQCTL_SELGPU(IRQ_GPU_TIMER1) | IRQ_FIQCTL_ENABLE;
33 IRQ_ENABLE1_REG |= 1 << irq;
35 IRQ_ENABLE2_REG |= 1 << (irq - 32);
40 void disable_gpu_irq(int irq)
43 if(irq == IRQ_GPU_TIMER1) {
46 IRQ_ENABLE1_REG &= ~(1 << irq);
48 IRQ_ENABLE2_REG &= ~(1 << (irq - 32));