6 #define IOREG(offs) (*(volatile uint32_t*)(rpi_iobase | offs))
9 #define STM_CTL_REG IOREG(0x3000)
10 #define STM_STAT_REG STM_CTL_REG
11 #define STM_LCNT_REG IOREG(0x3004)
12 #define STM_HCNT_REG IOREG(0x3008)
13 #define STM_CMP0_REG IOREG(0x300c)
14 #define STM_CMP1_REG IOREG(0x3010)
15 #define STM_CMP2_REG IOREG(0x3014)
16 #define STM_CMP3_REG IOREG(0x3018)
24 #define TM_LOAD_REG IOREG(0xb400)
25 #define TM_VALUE_REG IOREG(0xb404)
26 #define TM_CTL_REG IOREG(0xb408)
27 #define TM_ICLR_REG IOREG(0xb40c)
28 #define TM_IRAW_REG IOREG(0xb410)
29 #define TM_IMSK_REG IOREG(0xb414)
30 #define TM_RELOAD_REG IOREG(0xb418)
31 #define TM_PREDIV_REG IOREG(0xb41c)
32 #define TM_COUNT_REG IOREG(0xb420)
34 #define TMCTL_23BIT 0x000002
35 #define TMCTL_DIV16 0x000004
36 #define TMCTL_DIV256 0x000008
37 #define TMCTL_DIV1 0x00000c
38 #define TMCTL_IEN 0x000020
39 #define TMCTL_EN 0x000080
40 #define TMCTL_DBGHALT 0x000100
41 #define TMCTL_CNTEN 0x000200
43 #define TMCTL_PRESCALER(x) (((uint32_t)(x) & 0xff) << 16)
46 #define PM_RSTC_REG IOREG(0x10001c)
47 #define PM_WDOG_REG IOREG(0x100024)
49 #define PM_PASSWD 0x5a000000
50 #define PMRSTC_WRCFG_FULL_RESET 0x00000020
51 #define PMRSTC_WRCFG_CLEAR 0xffffffcf
54 #define MBOX_READ_REG IOREG(0xb880)
55 #define MBOX_POLL_REG IOREG(0xb890)
56 #define MBOX_SENDER_REG IOREG(0xb894)
57 #define MBOX_STATUS_REG IOREG(0xb898)
58 #define MBOX_CFG_REG IOREG(0xb89c)
59 #define MBOX_WRITE_REG IOREG(0xb8a0)
61 /* the full bit is set when there's no space to append messages */
62 #define MBOX_STAT_FULL 0x80000000
63 /* the empty bit is set when there are no pending messages to be read */
64 #define MBOX_STAT_EMPTY 0x40000000
67 #define IRQ_PENDING0_REG IOREG(0xb200)
68 #define IRQ_PENDING1_REG IOREG(0xb204)
69 #define IRQ_PENDING2_REG IOREG(0xb208)
70 #define IRQ_FIQCTL_REG IOREG(0xb20c)
71 #define IRQ_ENABLE1_REG IOREG(0xb210)
72 #define IRQ_ENABLE2_REG IOREG(0xb214)
73 #define IRQ_ENABLE0_REG IOREG(0xb218)
74 #define IRQ_DISABLE1_REG IOREG(0xb21c)
75 #define IRQ_DISABLE2_REG IOREG(0xb220)
76 #define IRQ_DISABLE0_REG IOREG(0xb224)
87 #define IRQ_GPU_TIMER0 0
88 #define IRQ_GPU_TIMER1 1
89 #define IRQ_GPU_TIMER2 2
90 #define IRQ_GPU_TIMER3 3
91 #define IRQ_GPU_AUX 29
92 #define IRQ_GPU_I2C_SPI_SLV 43
93 #define IRQ_GPU_PWA0 45
94 #define IRQ_GPU_PWA1 46
95 #define IRQ_GPU_SMI 48
96 #define IRQ_GPU_GPIO0 49
97 #define IRQ_GPU_GPIO1 50
98 #define IRQ_GPU_GPIO2 51
99 #define IRQ_GPU_GPIO3 52
100 #define IRQ_GPU_I2C 53
101 #define IRQ_GPU_SPI 54
102 #define IRQ_GPU_PCM 55
103 #define IRQ_GPU_UART 57
105 /* IRQ_PENDING0_REG flags (pending basic interrupts) */
106 #define IRQ_PEND0_TIMER 0x0000001
107 #define IRQ_PEND0_MBOX 0x0000002
108 #define IRQ_PEND0_DOORB0 0x0000004
109 #define IRQ_PEND0_DOORB1 0x0000008
110 #define IRQ_PEND0_GPU0HLT 0x0000010
111 #define IRQ_PEND0_GPU1HLT 0x0000020
112 #define IRQ_PEND0_ILL1 0x0000040
113 #define IRQ_PEND0_ILL0 0x0000080
114 #define IRQ_PEND0_PEND2 0x0000100
115 #define IRQ_PEND0_PEND1 0x0000200
116 #define IRQ_PEND0_GPU_IRQ7 0x0000400
117 #define IRQ_PEND0_GPU_IRQ9 0x0000800
118 #define IRQ_PEND0_GPU_IRQ10 0x0001000
119 #define IRQ_PEND0_GPU_IRQ18 0x0002000
120 #define IRQ_PEND0_GPU_IRQ19 0x0004000
121 #define IRQ_PEND0_GPU_I2C 0x0008000
122 #define IRQ_PEND0_GPU_SPI 0x0010000
123 #define IRQ_PEND0_GPU_PCM 0x0020000
124 #define IRQ_PEND0_GPU_IRQ56 0x0040000
125 #define IRQ_PEND0_GPU_UART 0x0080000
126 #define IRQ_PEND0_GPU_IRQ62 0x0100000
129 #define IRQ_FIQCTL_SELGPU(x) (x)
130 #define IRQ_FIQCTL_SELARM(x) ((x) + 64)
131 #define IRQ_FIQCTL_ENABLE 0x80
133 #endif /* RPI_IOREG_H_ */