4 /* c7 reg, op1=0, mode c14 is clean&inval, op2=1 is cacheline MVA */
5 #define sysctl_dcache_clean_inval(addr, len) \
7 register uint32_t a asm("r0") = addr; \
9 "\n0:\tmcr p15, 0, %0, c7, c14, 1" \
13 :: "r"(a), "r"(addr + len) \
17 #define sysctl_icache_inval(addr, len) \
19 register uint32_t a asm("r0") = addr; \
21 "\n0:\tmcr p15, 0, %0, c7, c5, 1" \
25 :: "r"(a), "r"(addr + len) \
29 #endif /* SYSCTL_H_ */