git.mutantstargoat.com Git - snes_test1/blob - hwregs.inc

   1         ; PPU write-only
   2         REG_INIDISP     = $2100
   3         REG_OBSEL       = $2101
   4         REG_OAMADDL     = $2102
   5         REG_OAMADDH     = $2103
   6         REG_OAMDATA     = $2104
   7         REG_BGMODE      = $2105
   8         REG_MOSAIC      = $2106
   9         REG_BG1SC       = $2107
  10         REG_BG2SC       = $2108
  11         REG_BG3SC       = $2109
  12         REG_BG4SC       = $210a
  13         REG_BG12NBA     = $210b
  14         REG_BG34NBA     = $210c
  15         REG_BG1HOFS     = $210d
  16         REG_BG1VOFS     = $210e
  17         REG_BG2HOFS     = $210f
  18         REG_BG2VOFS     = $2110
  19         REG_BG3HOFS     = $2111
  20         REG_BG3VOFS     = $2112
  21         REG_BG4HOFS     = $2113
  22         REG_BG4VOFS     = $2114
  23         REG_VMAINC      = $2115
  24         REG_VMADDL      = $2116
  25         REG_VMADDH      = $2117
  26         REG_VMDATAL     = $2118
  27         REG_VMDATAH     = $2119
  28         REG_M7SEL       = $211a
  29         REG_M7A         = $211b
  30         REG_M7B         = $211c
  31         REG_M7C         = $211d
  32         REG_M7D         = $211e
  33         REG_M7X         = $211f
  34         REG_M7Y         = $2120
  35         REG_CGADD       = $2121
  36         REG_CGDATA      = $2122
  37         REG_W12SEL      = $2123
  38         REG_W34SEL      = $2124
  39         REG_WOBJSEL     = $2125
  40         REG_WH0         = $2126
  41         REG_WH1         = $2127
  42         REG_WH2         = $2128
  43         REG_WH3         = $2129
  44         REG_WBGLOG      = $212a
  45         REG_WOBJLOG     = $212b
  46         REG_TM          = $212c
  47         REG_TS          = $212d
  48         REG_TMW         = $212e
  49         REG_TSW         = $212f
  50         REG_CGWSEL      = $2130
  51         REG_CGADSUB     = $2131
  52         REG_COLDATA     = $2132
  53         REG_SETINI      = $2133
  54         ; PPU read-only
  55         REG_MPYL        = $2134
  56         REG_MPYM        = $2135
  57         REG_MPYH        = $2136
  58         REG_SLHV        = $2137
  59         REG_RDOAM       = $2138
  60         REG_RDVRAML     = $2139
  61         REG_RDVRAMH     = $213a
  62         REG_RDCGRAM     = $213b
  63         REG_OPHCT       = $213c
  64         REG_OPVCT       = $213d
  65         REG_STAT77      = $213e
  66         REG_STAT78      = $213f
  67
  68         REG_NMITIMEN    = $4200
  69         REG_WRIO        = $4201
  70         REG_WRMPYA      = $4202
  71         REG_WRMPYB      = $4203
  72         REG_WRDIVL      = $4204
  73         REG_WRDIVH      = $4205
  74         REG_WRDIVB      = $4206
  75         REG_HTIMEL      = $4207
  76         REG_HTIMEH      = $4208
  77         REG_VTIMEL      = $4209
  78         REG_VTIMEH      = $420a
  79         REG_MEMSEL      = $420d
  80
  81         ; DMA
  82         REG_MDMAEN      = $420b
  83         REG_HDMAEN      = $420c
  84
  85         REG_HVBJOY      = $4212
  86
  87         REG_DMAP_BASE   = $4300
  88         REG_BBAD_BASE   = $4301
  89         REG_A1TL_BASE   = $4302
  90         REG_A1TH_BASE   = $4303
  91         REG_A1B_BASE    = $4304
  92         REG_DASL_BASE   = $4305
  93         REG_DASH_BASE   = $4306
  94         REG_DASB_BASE   = $4307
  95         REG_A2AL_BASE   = $4308
  96         REG_A2AH_BASE   = $4309
  97         REG_NTRL_BASE   = $430a
  98
  99         .define REG_DMAP(n)     REG_DMAP_BASE | (n << 4)
 100         .define REG_BBAD(n)     REG_BBAD_BASE | (n << 4)
 101         .define REG_A1TL(n)     REG_A1TL_BASE | (n << 4)
 102         .define REG_A1TH(n)     REG_A1TH_BASE | (n << 4)
 103         .define REG_A1B(n)      REG_A1B_BASE | (n << 4)
 104         .define REG_DASL(n)     REG_DASL_BASE | (n << 4)
 105         .define REG_DASH(n)     REG_DASH_BASE | (n << 4)
 106         .define REG_DASB(n)     REG_DASB_BASE | (n << 4)
 107         .define REG_A2AL(n)     REG_A2AL_BASE | (n << 4)
 108         .define REG_A2AH(n)     REG_A2AH_BASE | (n << 4)
 109         .define REG_NTRL(n)     REG_NTRL_BASE | (n << 4)
 110
 111
 112         .macro setreg reg, val
 113         lda #val
 114         sta reg
 115         .endmacro
 116
 117         .macro fblank onoff
 118         lda #($0f | (onoff << 7))
 119         sta REG_INIDISP
 120         .endmacro
 121
 122         .macro setpal idx, r, g, b
 123         setreg REG_CGADD, idx
 124         setreg REG_CGDATA, (r | g << 5)
 125         setreg REG_CGDATA, (g >> 3 | b << 2)
 126         .endmacro
 127
 128         .macro wait_vblank
 129 @wait_vblank_loop:
 130         lda REG_HVBJOY
 131         and #$80
 132         beq @wait_vblank_loop
 133         .endmacro
 134
 135         ; vi:ft=asm_ca65: